异构集成互连接口研究综述

李沛杰; 刘勤让; 陈艇; 沈剑良; 吕平; 郭威

doi:10.20193/j.ices2097-4191.2024.02.004

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集成电路与嵌入式系统 ›› 2024, Vol. 24 ›› Issue (2) : 31-40. DOI: 10.20193/j.ices2097-4191.2024.02.004

Chiplet研究专栏

异构集成互连接口研究综述

作者信息 +

Research on the heterogeneous integrated interconnect interface

Author information +

文章历史 +

摘要

随着集成电路向后摩尔时代发展,异构集成技术成为微电子的新兴方向,异构集成互连接口作为异构集成技术的关键,对异构集成芯片和系统至关重要。为进一步推进异构集成互连接口的实现,分析了现有异构集成芯片和系统的结构,将异构集成技术总结为小芯粒拼接大芯片、大芯片拼接大芯片、晶圆级芯片及晶圆级系统4个技术路线,并对不同技术路线下异构集成互连接口特性进行了总结和对比,阐述了当前产业界和学术界围绕异构集成互连接口的研究现状及存在的问题,最后给出了异构集成互连接口的未来发展趋势和需具备的技术特征。

Abstract

With the development of integrated circuits to the Beyond Moor era,the heterogeneous integration technology has become an emerging direction of microelectronics.The interconnect interface,the key to the heterogeneous integration technology, is critical to heterogeneous integrated chip and system.In order to promote the implementation of heterogeneous integrated interconnect interface, the structure of the heterogeneous integrated chip and system is described and the heterogeneous integration technology is summarized into four technical routes:large chip by integrated chiplets, larger chip by integrated large chips,wafer-level chips and wafer-level systems. The characteristics of the heterogeneous integrated interconnect interface are summarized.The current research status and existing problems in the industry and academia around the heterogeneous integrated interconnect interface are analyzed.Finally,the future development trend and the needed technical characteristics of the heterogeneous integrated interconnect interface are given by this article.

导出引用

李沛杰, 刘勤让, 陈艇, 等. 异构集成互连接口研究综述[J]. 集成电路与嵌入式系统. 2024, 24(2): 31-40 https://doi.org/10.20193/j.ices2097-4191.2024.02.004

LI Peijie, LIU Qinrang, CHEN Ting, et al. Research on the heterogeneous integrated interconnect interface[J]. Integrated Circuits and Embedded Systems. 2024, 24(2): 31-40 https://doi.org/10.20193/j.ices2097-4191.2024.02.004

中图分类号： TP303 (总体结构、系统结构)

参考文献

列表( 原文顺序 | 文献年度倒序 | 文中引用次数倒序 ) 可视化分析

[1]	吴林晟, 毛军发. 从集成电路到集成系统[J]. 中国科学:信息科学, 2023(53):1843-1857. WU L SH, MAO J F. From Integrated Circuits to Integrated Systems[J]. Chinese Science:Information Science, 2023(53):1843-1857. 本文引用 [1]

[2]	OLOFSSON A, GREEN D S, DEMMIN J. Enabling High-Performance Heterogeneous Integration via Interface Standards,IP Reuse,and Modular Design[J]. International Symposium on Microelectronics, 2018(1):246-251. 本文引用 [1]

[3]

, HOU

, YAN

, et al. Chiplet heterogeneous integration technology-Status and challenges[J]. Electronics, 2020, 9(4):670.

https://doi.org/10.3390/electronics9040670

https://www.mdpi.com/2079-9292/9/4/670

本文引用 [1] 摘要

As a heterogeneous integration technology, the chiplet-based design technology integrates multiple heterogeneous dies of diverse functional circuit blocks into a single chip by using advanced packaging technology, which is a promising way to tackle the failure of Moore’s law and Dennard scaling. Currently, as process nodes move forward, dramatically rising cost, design cycle, and complexity are driving industry to focus on the chiplets. Chiplets allows IC designers to merge dies fabricated at different process nodes and reuse them in different projects, which helps to reduce the cost during design and improve yield. In this review, we look back at the industry’s efforts over the past decade and summary the concepts and techniques associated with chiplets. In the end, a discussion and conclusion will be given to forecast the future of chiplets.

[4]	TEWKSBURY S K. Wafer-level integrated systems: implementation issues[M].Springer Science & Business Media, 2012. 本文引用 [1]

[5]

SHARMA

D D

, PASDAST

, QIAN

, et al. Universal chiplet interconnect express (UCIe):An open industry standard for innovations with chiplets at package level[J]. IEEE Transactions on Components, Packaging and Manufacturing Technology, 2022, 12(9):1423-1431.

https://doi.org/10.1109/TCPMT.2022.3207195

https://ieeexplore.ieee.org/document/9893865/

本文引用 [1]

[6]	IYER S S, JANGAM S, VAISBAND B. Silicon interconnect fabric: A versatile heterogeneous integration platform for AI systems[J]. IBM Journal of Research and Development, 2019, 63(6):1-5. 本文引用 [1]

[7]	JANGAM S C, PAL S, BAJWA A, et al. Latency, bandwidth and power benefits of the superchips integration scheme[C]// 2017 IEEE 67th Electronic Components and Technology Conference (ECTC).IEEE, 2017:86-94. 本文引用 [1]

[8]	VAISBAND B, IYER S S. Global and semi-global communication on Si-IF[C]// Proceedings of the 13th IEEE/ACM International Symposium on Networks-on-Chip, 2019:1-5. 本文引用 [1]

[9]	SAFARI Y, KROON A, VAISBAND B. Power Delivery for Ultra-Large-Scale Applications on Si-IF[C]// 2022 IEEE International Symposium on Circuits and Systems (ISCAS).IEEE, 2022:1605-1609. 本文引用 [1]

[10]	MAHAJAN R, SANKMAN R, PATEL N, et al. Embedded multi-die interconnect bridge (EMIB)-a high density,high bandwidth packaging interconnect[C]// 2016 IEEE 66th Electronic Components and Technology Conference (ECTC).IEEE, 2016:557-565. 本文引用 [1]

[11]	INGERLY D B, AMIN S, ARYASOMAYAJULA L, et al. Foveros:3D integration and the use of face-to-face chip stacking for logic devices[C]// 2019 IEEE International Electron Devices Meeting (IEDM).IEEE, 2019:19.6.1-19.6. 4. 本文引用 [1]

[12]	ELSHERBINI A A, LIFF S M, SWAN J M. Heterogeneous integration using omni-directional interconnect packaging[C]// 2019 IEEE International Electron Devices Meeting (IEDM).IEEE, 2019:19.4.1-19.4. 4. 本文引用 [1]

[13]

ONG

J J

, CHIU

W L

, LEE

O H

, et al. Low-temperature Cu/SiO₂ hybrid bonding with low contact resistance using (111)-oriented Cu surfaces[J]. Materials, 2022, 15(5):1888.

https://doi.org/10.3390/ma15051888

https://www.mdpi.com/1996-1944/15/5/1888

本文引用 [1] 摘要

We adopted (111)-oriented Cu with high surface diffusivity to achieve low-temperature and low-pressure Cu/SiO2 hybrid bonding. Electroplating was employed to fabricate arrays of Cu vias with 78% (111) surface grains. The bonding temperature can be lowered to 200 °C, and the pressure is as low as 1.06 MPa. The bonding process can be accomplished by a 12-inch wafer-to-wafer scheme. The measured specific contact resistance is 1.2 × 10−9 Ω·cm2, which is the lowest value reported in related literature for Cu-Cu joints bonded below 300 °C. The joints possess excellent thermal stability up to 375 °C. The bonding mechanism is also presented to provide more understanding on hybrid bonding.

[14]	YIP L, TSAI J, LIN R, et al. 2.5 D MCM (Multi-chip Module) Technology Development for Advanced Package[C]// 2023 IEEE 73rd Electronic Components and Technology Conference (ECTC).IEEE, 2023:778-782. 本文引用 [1]

[15]	HU Y C, LIANG Y M, HU H P, et al. CoWoS Architecture Evolution for Next Generation HPC on 2.5D System in Package[C]// 2023 IEEE 73rd Electronic Components and Technology Conference (ECTC).IEEE, 2023:1022-1026. 本文引用 [1]

[16]	TSENG C F, LIU C S, WU C H, et al. InFO (wafer level integrated fan-out) technology[C]// 2016 IEEE 66th Electronic Components and Technology Conference (ECTC).IEEE, 2016:1-6. 本文引用 [1]

[17]	CHEN M F, CHEN F C, CHIOU W C, et al. System on integrated chips (SoIC for 3D heterogeneous integration[C]// 2019 IEEE 69th Electronic Components and Technology Conference (ECTC).IEEE, 2019:594-599. 本文引用 [1]

[18]	LAUTERBACH G. The path to successful wafer-scale integration:The cerebras story[J]. IEEE Micro, 2021, 41(6):52-57. https://doi.org/10.1109/MM.2021.3112025 https://ieeexplore.ieee.org/document/9623424/ 本文引用 [1]

[19]	LIU H, GAO C, WU Q T. Study on Inter-Layer Overlay of Stitching Lithography Technology[C]// 2023 China Semiconductor Technology International Conference (CSTIC).IEEE, 2023:1-3. 本文引用 [1]

[20]	JO P K, HOSSEN M O, ZHANG X, et al. Heterogeneous multi-die stitching: Technology demonstration and design considerations[C]// 2018 IEEE 68th Electronic Components and Technology Conference (ECTC).IEEE, 2018:1512-1518. 本文引用 [1]

[21]	VARDAMAN J, HUNT J. Fan Out for Advanced Packaging Applications[C]// ISTFA 2023. ASM International, 2023:a1-a63. 本文引用 [1]

[22]	TALPES E, WILLIAMS D, SARMA D D. Dojo:The microarchitecture of tesla’s exa-scale computer[C]// 2022 IEEE Hot Chips 34 Symposium (HCS).IEEE Computer Society, 2022:1-28. 本文引用 [1]

[23]	PAL S, LIU J, ALAM I, et al. Designing a 2048-chiplet, 14336-core waferscale processor[C]// 2021 58th ACM/IEEE Design Automation Conference (DAC).IEEE, 2021:1183-1188. 本文引用 [1]

[24]	IYER S S. Heterogeneous integration using the silicon interconnect fabric[C]// 2018 IEEE 2nd Electron Devices Technology and Manufacturing Conference (EDTM).IEEE, 2018:135-137. 本文引用 [1]

[25]	PAL S, ALAM I, SAHOO K, et al. I/O Architecture, Substrate Design, and Bonding Process for a Heterogeneous Dielet-Assembly based Waferscale Processor[C]//2021 IEEE 71st Electronic Components and Technology Conference (ECTC).IEEE, 2021:298-303. 本文引用 [1]

[26]	THANKAPPAN K K, BAJWA A, VAISBAND B, et al. Reliability Evaluation of Silicon Interconnect Fabric Technology[C]// 2019 IEEE International Reliability Physics Symposium (IRPS).IEEE, 2019:1-5. 本文引用 [1]

[27]	邬江兴, 刘勤让, 汤先拓, 等. 软件定义晶上系统及数据交互方法和系统体系架构[P].河南省:CN112800715B,2021-09-24. WU J X, LIU Q R, TANG X T, et al. Software Defined Crystal System and Data Interaction Methods and System Architecture[P].Henan Province:CN112800715B,2021-09-24 (in Chinese). 本文引用 [1]

[28]	邬江兴, 刘勤让, 魏帅, 等. 晶上系统开发环境搭建方法及系统[P].河南省:CN112506496B,2021-08-03. WU J X, LIU Q R, WEI SH, et al. Methods and Systems for Building the Development Environment of Jingshang System[P].Henan Province:CN112506496B,2021-08-03 (in Chinese). 本文引用 [1]

[29]	刘勤让, 邬江兴, 吕平, 等. 一种晶上软件定义互连网络装置与方法[P].河南省:CN112562767B,2021-09-28. LIU Q R, WU J X, LV P. A Crystal Software Defined Interconnection Network Device and Method[P].Henan Province:CN112562767B,2021-09-28 (in Chinese). 本文引用 [1]

[30]	Synopsys. Synopsys Die-to-Die IP Solutions[EB/OL].[2024-01-05]. https://www.synopsys.com/designware-ip/interface-ip/die-to-die.html, 2021. https://www.synopsys.com/designware-ip/interface-ip/die-to-die.html 本文引用 [1]

[31]	LI A, SONG S L, CHEN J, et al. Evaluating modern gpu interconnect:Pcie,nvlink, nv-sli,nvswitch and gpudirect[J]. IEEE Transactions on Parallel and Distributed Systems, 2019, 31(1):94-110. https://doi.org/10.1109/TPDS.71 https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=71 本文引用 [1]

[32]	CCIX Consortium. Cache coherent interconnect for accelerators (CCIX)[EB/OL].[2024-01-05]. http://www.ccixconsortium.com, 2017. http://www.ccixconsortium.com 本文引用 [1]

[33]	Intel. Advanced Interface Bus (AIB) Specifications[EB/OL].[2024-01-05]. https://github.com/chipsalliance/AIB-specification, 2019. https://github.com/chipsalliance/AIB-specification 本文引用 [1]

[34]	LIN M S, HUANG T C, TSAI C C, et al. A 7-nm 4-GHz Arm-core-based CoWoS chiplet design for high-performance computing[J]. IEEE Journal of Solid-State Circuits, 2020, 55(4):956-966. https://doi.org/10.1109/JSSC.4 https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=4 本文引用 [1]

[35]	JUN H, CHO J, LEE K, et al. Hbm (high bandwidth memory) dram technology and architecture[C]// 2017 IEEE International Memory Workshop (IMW).IEEE, 2017:1-4. 本文引用 [1]

[36]	AMD. Introducing AMD CDNA 2 architecture[EB/OL].[2024-01-05]. https://www.amd.com/system/files/documents/amd-cdna2-white-paper.pdf, 2021. https://www.amd.com/system/files/documents/amd-cdna2-white-paper.pdf 本文引用 [1]

[37]	ARDALAN S, CIRIT H, FARJAD R, et al. Bunch of wires:An open die-to-die interface[C]// 2020 IEEE Symposium on High-Performance Interconnects (HOTI).IEEE, 2020:9-16. 本文引用 [1]

[38]	JANGAM S C, PAL S, BAJWA A, et al. Latency,bandwidth and power benefits of the superchips integration scheme[C]// 2017 IEEE 67th Electronic Components and Technology Conference (ECTC).IEEE, 2017:86-94. 本文引用 [1]