一款400 μm2用于极短距离接收机具有中频补偿的56 Gb/s PAM4反相器型连续时间线性均衡器

王梦豪, 赵潇腾, 董志成, 张淼, 刘术彬, 朱樟明

集成电路与嵌入式系统 ›› 2024, Vol. 24 ›› Issue (3) : 27-34.

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集成电路与嵌入式系统 ›› 2024, Vol. 24 ›› Issue (3) : 27-34. DOI: 10.20193/j.ices2097-4191.2024.03.006
研究论文

一款400 μm2用于极短距离接收机具有中频补偿的56 Gb/s PAM4反相器型连续时间线性均衡器

作者信息 +

A 400 μm2 56 Gb/s PAM4 inverter-based CTLE with mid-frequency compensation for extra short reach receivers

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摘要

高速极短距离有线数据接口是芯粒间互连的重要技术方案。传统的基于电流模逻辑的连续时间线性均衡器由于高电源电压和无源器件的使用已经无法满足芯粒间数据接口高密度、小型化、低功耗的需求。针对该问题,本文提出了一种带中频补偿的反相器型连续时间线性均衡器,可在极短距离应用中传输28 Gb/s非归零信号以及56 Gb/s四电平脉冲幅度调制信号。本设计采用28 nm CMOS工艺实现,核心面积仅为400 μm2。经过-9.4 dB@14 GHz的极短距离信道后,基于版图的仿真结果表明,所提出的连续时间线性均衡器使28 Gbaud的非归零信号与四电平脉冲幅度调制信号眼宽分别提升0.14 UI与0.41 UI,眼高提升328 mV与119 mV,56 Gb/s 四电平脉冲幅度调制信号工况下功耗为6.12 mW。

Abstract

High-speed extra short reach (XSR) wireline interfaces are an important technical solution for chiplets interconnection.The traditional continuous time linear equalizer (CTLE) based on current mode logic (CML) has gradually failed to meet the demand for high-density,miniaturization,and low-power consumption of chiplet data interfaces due to the use of high supply voltage and passive components.To address this problem,this paper proposes an inverter-based CTLE with mid-frequency compensation (MFC) to transmit 28 Gb/s non-return to zero (NRZ) signals as well as 56 Gb/s 4-level pulse amplitude modulation (PAM4) signals in XSR applications.The design is implemented in a 28 nm CMOS process with a core area of only 400 μm2.After an XSR channel at -9.4 dB@14 GHz,the post-layout simulation results show that the proposed CTLE improves the eye width of the 28 Gbaud NRZ and PAM4 signals by 0.14 UI and 0.41 UI,and the eye heights by 328 mV and 119 mV,respectively.The power consumption is 6.12 mW at 56 Gb/s PAM4 signaling.

关键词

连续时间线性均衡器 / 反相器型 / 有源电感负载 / 中频补偿 / 四电平脉冲幅度调制 / 芯粒

Key words

CTLE / inverter-based / active inductive load / mid-frequency compensation / PAM4 / Chiplet

引用本文

导出引用
王梦豪, 赵潇腾, 董志成, . 一款400 μm2用于极短距离接收机具有中频补偿的56 Gb/s PAM4反相器型连续时间线性均衡器[J]. 集成电路与嵌入式系统. 2024, 24(3): 27-34 https://doi.org/10.20193/j.ices2097-4191.2024.03.006
WANG Menghao, ZHAO Xiaoteng, DONG Zhicheng, et al. A 400 μm2 56 Gb/s PAM4 inverter-based CTLE with mid-frequency compensation for extra short reach receivers[J]. Integrated Circuits and Embedded Systems. 2024, 24(3): 27-34 https://doi.org/10.20193/j.ices2097-4191.2024.03.006
中图分类号: TN43 (半导体集成电路(固体电路))   

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基金

高能效多电平宽范围高速数据接口接收机关键技术研究(62374126)
高效模拟前端集成电路和集成系统(62021004)
超高速模数转换器集成电路测试验证系统(62227816)
高速射频模数转换器芯片研究(2022YFB4401900)

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