GPIO引脚模拟I2C通信的驱动设计

韩勇; 张芬; 魏进松; 于涛

doi:10.20193/j.ices2097-4191.2024.04.015

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集成电路与嵌入式系统 ›› 2024, Vol. 24 ›› Issue (4) : 82-87. DOI: 10.20193/j.ices2097-4191.2024.04.015

研究论文

GPIO引脚模拟I²C通信的驱动设计

作者信息 +

Driver design for simulating I²C communication based on GPIO pins

Author information +

文章历史 +

摘要

I²C总线多用于嵌入式系统中多个芯片及模块间的数据通信,针对芯片的I²C总线专用引脚被占用或I²C总线功能需移植到其他平台等需求,现有的I²C总线专用引脚使用方式存在一定的局限性。本文基于I²C总线的通信机理开发了一套驱动程序,通过控制常规GPIO引脚电平模拟I²C时序,实现I²C总线通信功能。以STM32F103C8T6芯片为I²C总线主控制器、PCF8591T A/D转换模块为I²C总线从器件,对开发的I²C驱动程序进行验证,试验结果表明,该驱动方式可靠、稳定。

Abstract

The I²C bus is widely employed for exchanging data between multiple chips and modules in embedded systems.However,the utilization of dedicated I²C bus pins has limitations when these pins are already occupied or when the I²C bus function needs to be migrated to other platforms.In the study,a driver program is developed that leverages the communication mechanism of the I²C bus.It achieves I²C bus communication functionality by simulating I²C timing through the control of electrical levels on conventional GPIO pins.The STM32F103C8T6 chip serves as the primary controller of the I²C bus,while the PCF8591T A/D conversion module operates as the slave device.This article verifies the developed I²C driver program,and the experimental results show that the driving method is reliable and stable.

导出引用

韩勇, 张芬, 魏进松, 等. GPIO引脚模拟I²C通信的驱动设计[J]. 集成电路与嵌入式系统. 2024, 24(4): 82-87 https://doi.org/10.20193/j.ices2097-4191.2024.04.015

HAN Yong, ZHANG Fen, WEI Jinsong, et al. Driver design for simulating I²C communication based on GPIO pins[J]. Integrated Circuits and Embedded Systems. 2024, 24(4): 82-87 https://doi.org/10.20193/j.ices2097-4191.2024.04.015

中图分类号： TP311.1 (程序设计)

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