电磁脉冲应力下MOSFET器件退化机制研究

宋斌斌, 王凯, 鹿祥宾, 单书珊, 罗宗兰, 栗磊, 赫嘉楠

集成电路与嵌入式系统 ›› 2024, Vol. 24 ›› Issue (5) : 55-59.

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集成电路与嵌入式系统 ›› 2024, Vol. 24 ›› Issue (5) : 55-59. DOI: 10.20193/j.ices2097-4191.2024.05.007
研究论文

电磁脉冲应力下MOSFET器件退化机制研究

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Study on degradation mechanism of MOSFET devices under electromagnetic pulse stress

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摘要

针对电力应用场景中电磁脉冲导致芯片性能异常退化、芯片内MOSFET(Metal-Oxide-Semiconductor Field-Effect Transistor)等器件失效机理不清晰等问题,本研究采用幅值和宽度分别为8 V和100 ns的TLP(Transmission Line Pulse)脉冲施加至5 V NMOS器件栅氧层,测量了不同脉冲循环次数下器件输出特性曲线Id-Vd和转移特性曲线Id-Vg,通过分析不同TLP脉冲条件下跨导的变化规律研究了阈值电压和载流子迁移率随TLP脉冲个数的退化规律。研究结果表明,相同漏电压Vd和栅极电压Vg下,器件漏电流Id随TLP脉冲次数的增加而升高;TLP脉冲导致阈值电压VT降低显著,施加20 000次TLP脉冲后VT降低约25.66%;TLP脉冲造成器件阈值电压的变化量呈指数升高,通过拟合指数为0.11~0.15;TLP脉冲对沟道内载流子迁移率的影响不明显。

Abstract

In response to issues such as abnormal degradation of chip performance caused by electromagnetic pulses in power application scenarios,and unclear failure mechanisms of devices such as MOSFET(Metal-Oxide-Semiconductor Field-Effect Transistors) within the chip,TLP (Transmission Line Pulse) pulses,with amplitude and width of 8 V and 100 ns,are applied into gate oxide layer of 5 V NMOS devices.The output characteristic curves Id-Vd and the transfer characteristic curves Id-Vg under different pulse cycles are measured.By calculating the device transconductance under different TLP number,the threshold voltage VT and carrier mobility with TLP pulse are obtained.The test results show that under the same drain voltage Vd and gate voltage Vg, the drain current Id of the device increases with the increase of the number of TLP pulses.TLP pulses cause a significant decrease of VT,which decreases by about 25.66% under 20 000 TLP pulses,TLP pulses caused the VT of the device to increase exponentially,and the fitting index is between 0.11~0.15.The influence of TLP pulses on the carrier mobility in the channel is not obvious.

关键词

金属氧化物半导体场效应管 / 电磁脉冲 / 阈值电压 / 跨导 / 迁移率

Key words

MOSFET / electromagnetic pulse / threshold voltage / transconductance / mobility

引用本文

导出引用
宋斌斌, 王凯, 鹿祥宾, . 电磁脉冲应力下MOSFET器件退化机制研究[J]. 集成电路与嵌入式系统. 2024, 24(5): 55-59 https://doi.org/10.20193/j.ices2097-4191.2024.05.007
SONG Binbin, WANG Kai, LU Xiangbin, et al. Study on degradation mechanism of MOSFET devices under electromagnetic pulse stress[J]. Integrated Circuits and Embedded Systems. 2024, 24(5): 55-59 https://doi.org/10.20193/j.ices2097-4191.2024.05.007
中图分类号: TN386   

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基金

国家电网有限公司总部科技项目(5100-202335010A-1-1-ZN)

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