宇航用总线型上注刷新ASIC的设计

于栋, 刘琦, 韩志学, 王磊, 申一伟, 李阳

集成电路与嵌入式系统 ›› 2024, Vol. 24 ›› Issue (5) : 72-80.

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集成电路与嵌入式系统 ›› 2024, Vol. 24 ›› Issue (5) : 72-80. DOI: 10.20193/j.ices2097-4191.2024.05.010
研究论文

宇航用总线型上注刷新ASIC的设计

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Design of bus-based program upload-scrubbing ASIC for aerospace applications

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摘要

当前宇航任务中,SRAM型FPGA易受到单粒子效应的影响,造成非预期的功能失效。为消减单粒子效应的影响、减小FPGA在轨维护重复开发和测试的工作量,设计了一款支持多种总线、适配多型FPGA和存储器的上注刷新ASIC芯片,用于完成FPGA的程序加载、动态刷新、程序上注等操作。首先介绍了ASIC系统层级、模块层级设计、工作流程规划,并简述了ASIC抗单粒子原理。通过对通信协议的兼容设计,ASIC同时支持CAN总线、RS485总线;通过对FPGA配置位流结构分析,ASIC支持9种FPGA的加载和刷新,并实现国产兼容;通过对存储器数据格式转换,ASIC能够在BPI Flash、SPI Flash、PROM等多种存储器中存储配置位流;对刷新的触发、SEFI检测、刷新的执行进行了论述。对影响ASIC上注速度的因素进行了分析和仿真验证;使用原型验证板、ASIC验证板配合可插拔的FPGA、存储器上浮小板完成流片前后的各项功能验证,验证结果符合预期。评估刷新的效果并与其他在轨维护方案进行对比,总线型FPGA上注刷新ASIC具有一定优势,可以高效、 可靠地满足宇航FPGA的多种在轨维护需求。

Abstract

In current aerospace missions,the SRAM-based FPGA is susceptible to single-event effects,resulting in unexpected functional failures.In order to mitigate the impact of single-event effects and reduce the workload of repetitive design and testing,a bus-based FPGA program upload-scrubbing ASIC is designed.The ASIC supports multiple buses,adapts to various FPGAs,and is compatible with different memory types.It is utilized for tasks such as FPGA program loading,scrubbing,program upload,and other on-orbit maintenance operations.Firstly,the ASIC's system-level design,module-level design,and workflow planning are presented.The principle of ASIC resistance to single-event effects is briefly described.By designing compatible communication protocols,the ASIC simultaneously supports CAN bus and RS485 bus.By analyzing the FPGA configuration bitstream structure,the ASIC supports loading and scrubbing 9 types of FPGAs and achieves domestic compatibility.By converting the data format of memory,the ASIC can store the configuration bitstream in various memories,including BPI Flash,SPI Flash,PROM,and others.The triggering of scrubbing,SEFI detection,and execution of scrubbing are discussed.Analyzing and simulating the factors affecting the upload speed of the ASIC.Utilize prototype verification board,ASIC verification board,and pluggable FPGAs and memory floating small boards to complete various functional verifications before and after tape-out.The verification results are as expected.The effectiveness of the scrubbing is evaluated and compared with other on-orbit maintenance schemes.The bus-based program upload-scrubbing ASIC has certain advantages and can efficiently and reliably meet the various on-orbit maintenance requirements of aerospace FPGA.

关键词

单粒子效应 / FPGA / 动态刷新 / 程序上注 / ASIC设计

Key words

single event effect / FPGA / scrubbing / program-upload / ASIC design

引用本文

导出引用
于栋, 刘琦, 韩志学, . 宇航用总线型上注刷新ASIC的设计[J]. 集成电路与嵌入式系统. 2024, 24(5): 72-80 https://doi.org/10.20193/j.ices2097-4191.2024.05.010
YU Dong, LIU Qi, HAN Zhixue, et al. Design of bus-based program upload-scrubbing ASIC for aerospace applications[J]. Integrated Circuits and Embedded Systems. 2024, 24(5): 72-80 https://doi.org/10.20193/j.ices2097-4191.2024.05.010
中图分类号: TP2 (自动化技术及设备)   

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