为了进一步优化乘法器的性能,提高乘法运算单元的运算速率,本文基于Radix-4 Booth算法和Wallace树压缩结构提出了一种改进的16位有符号数乘法器。其特点包括优化Radix-4 Booth编码方式,有效减小部分积选择电路的面积;改进部分积计算过程,通过优化取反加1的方法直接生成被乘数的相反数,同时采用经典的符号位补偿算法使得部分积阵列变得规整易压缩;提出一种新型4-2压缩器,采用单个全加器处理压缩器的中间进位,针对每行部分积不同的数据特征,细化处理了Wallace树压缩结构,提高了部分积的压缩效率。基于SMIC 180 nm标准单元库进行了综合与验证,结果表明本文所设计的乘法器关键路径延时为3.94 ns,面积为16 246 μm²,相比于现有的乘法器,本文乘法器的运算速率和综合性能都得到显著提升。

To further optimize the performance of the multiplier and improve the operation speed of the multiplication unit,an improved 16-bit signed number multiplier is designed based on the Radix-4 Booth algorithm and Wallace tree compression structure.Its characteristics are:optimize the Radix-4 Booth encoding method to effectively reduce the area of partial product selection circuits.Improve the partial product calculation process by optimizing the inverse plus one method to directly generate the opposite of the multiplicand,at the same time,use the classic sign bit compensation algorithm to make the partial product array regular and easy to compress.A new type of 4-2 compressor is proposed,which uses a single full adder to process the middle carry of the compressor.The Wallace tree compression structure is refined to improve the compression efficiency of partial products for different data features in each row.Synthesis and verified based on SMIC 180 nm standard cell library,the results show that the critical path delay of the multiplier designed in this paper is 3.94 ns,with an area of 16 246 μm².Compared to existing multipliers,the computational speed and overall performance of the multiplier in this paper have been significantly improved.