基于深沟槽单次外延工艺超级结MOS器件耐压提升与优化

田俊; 付振; 张泉; 肖超; 张文敏; 王悦

doi:10.20193/j.ices2097-4191.2024.06.007

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集成电路与嵌入式系统 ›› 2024, Vol. 24 ›› Issue (6) : 46-54. DOI: 10.20193/j.ices2097-4191.2024.06.007

研究论文

基于深沟槽单次外延工艺超级结MOS器件耐压提升与优化

田俊 ¹^,²^,^* ,
付振 ¹^,² ,
张泉 ¹^,² ,
肖超 ¹^,² ,
张文敏 ¹^,² ,
王悦 ¹^,²

作者信息 +

Voltage enhancement and optimization of super junction MOS devices based on deep trench single epitaxial process

TIAN Jun ¹^,²^,^* ,
FU Zhen ¹^,² ,
ZHANG Quan ¹^,² ,
XIAO Chao ¹^,² ,
ZHANG Wenmin ¹^,² ,
WANG Yue ¹^,²

Author information +

文章历史 +

摘要

介绍了超级结MOS器件的一种主流工艺—深沟槽单次外延工艺,详细介绍了该工艺的工艺流程及特点。基于超级结MOS器件的电荷平衡原理,分析不同P柱浓度条件下器件击穿电压(Breakdown Voltage)的变化规律,揭示击穿电压(BV)偏低的原因,提出一种改善方案,最终通过实验验证该方案的可行性。

Abstract

In this paper,a mainstream technology for manufacturing super junction MOS (SJMOS) devices,namely the Deep Trench Single Epitaxial Process (DTSE),is introduced.And the flow and characteristics of DTSE are described in detail.Based on the charge balance principle of SJMOS,the variation of breakdown voltage (BV) under different P-pillar doping concentrations is analyzed,revealing the reasons for the low BV.A improvement solution is proposed,and its feasibility is demonstrated through the experimental verification.

导出引用

田俊, 付振, 张泉, 等. 基于深沟槽单次外延工艺超级结MOS器件耐压提升与优化[J]. 集成电路与嵌入式系统. 2024, 24(6): 46-54 https://doi.org/10.20193/j.ices2097-4191.2024.06.007

TIAN Jun, FU Zhen, ZHANG Quan, et al. Voltage enhancement and optimization of super junction MOS devices based on deep trench single epitaxial process[J]. Integrated Circuits and Embedded Systems. 2024, 24(6): 46-54 https://doi.org/10.20193/j.ices2097-4191.2024.06.007

中图分类号： TP31 (计算机软件)

参考文献

列表( 原文顺序 | 文献年度倒序 | 文中引用次数倒序 ) 可视化分析

[1]	包莉婷. 南方电网公司第四代充电桩产品在穗发布[J]. 新能源科技, 2022(7):32. BAO L T. China Southern Power Grid Corporation's fourth generation charging station product released in Guangzhou[J]. New Energy Technology, 2022(7):32. (in Chinese) 本文引用 [1]

[2]	KIM BUM JUNE, HONG YOUNG SUNG, SIM GWAN PIL, et al. Study on the Design of DC-DC Converter for Super Junction MOSFET Battery Charger of Electric Vehicles[J]. Journal of the Korean Institute of Electrical and Electronic Material Engineers, 2013, 26(8):587-590. 本文引用 [1]

[3]	ZHANG YUHAO, UDREA FLORIN, WANG HAN. Multidimensional device architectures for efficient power electronics[J]. Nature Electronics, 2022, 5(11):723-734. 本文引用 [1]

[4]	ZHANG BO, ZHANG WENTONG, QIAO MING, et al. Concept and design of super junction devices[J]. Journal of Semiconductors, 2018, 39(2):021001. 本文引用 [1]

[5]	杨法明, 杨发顺, 张锗源, 等. 功率VDMOS器件的研究与发展[J]. 微纳电子技术, 2011, 48(10):8. YANG F M, YANG F SH, ZHANG ZH Y, et al. Research and Development of Power VDMOS Devices[J]. Microelectronics and Nanoelectronics Technology, 2011, 48(10):8. (in Chinese) 本文引用 [1]

[6]	F UDREA, G DEBOY, T FUJIHIRA. Superjunction Power Devices, History,Development,and Future Prospects[J]. IEEE Transactions on Electron Devices, 2017, 64(3):713-727. 本文引用 [1]

[7]	陈星弼. 超结器件[J]. 电力电子技术, 2008, 42(12):2-7. CHEN X B. Superjunction Devices[J]. Power Electronics Technology, 2008, 42(12):2-7. (in Chinese) 本文引用 [1]

[8]	雷海波, 肖胜安, 刘继全, 等. 超级结深沟槽填充工艺及其对器件性能的影响[J]. 固体电子学研究与进展, 2014, 34(3):5. LEI H B, XIAO SH AN, LIU J Q, et al. Super junctionbased on deep trench filling process and its impact on device performance[J]. Solid State Electronics Research and Progress, 2014, 34(3):5. (in Chinese) 本文引用 [1]

[9]	姚亮, 王飞, 肖胜安. 深沟槽填充超结的电荷平衡对器件性能的影响[J]. 固体电子学研究与进展, 2016(3):5. YAO L, WANG F, XIAO SH AN. The effect of charge balance based on deep trench filled superjunctions on device performance[J]. Research and Progress in Solid State Electronics, 2016(3):5. (in Chinese) 本文引用 [1]