集成电路固有失效机理的可靠性评价综述

章晓文; 周斌; 牛皓; 林晓玲

doi:10.20193/j.ices2097-4191.2024.07.001

PDF(1892 KB)

集成电路与嵌入式系统 ›› 2024, Vol. 24 ›› Issue (7) : 1-11. DOI: 10.20193/j.ices2097-4191.2024.07.001

集成电路可靠性研究专栏

集成电路固有失效机理的可靠性评价综述

作者信息 +

Review on the reliability evaluation of inherent failure mechanism of integrated circuits

Author information +

文章历史 +

摘要

ULSI/VLSI集成电路芯片的可靠性既与设计有关,也与工艺加工过程有关,即芯片的可靠性是设计进去、制造出来。设计是集成电路芯片可靠性的基础,工艺制造是集成电路芯片可靠性的实现。要使超大规模集成电路在特定的寿命期间内能够稳定地工作,必须对影响集成电路芯片可靠性的固有失效机理进行评价。评价的目的是确定磨损失效的机理,通过改进设计和工艺加工水平确保集成电路芯片在整个产品寿命期间有良好的可靠性。本文梳理了国内外集成电路芯片固有失效机理的可靠性评价标准,阐述了这些固有失效机理的产生机制,总结了不同固有失效机理的试验方法,提出了固有失效机理的可靠性评价要求。这些标准、方法和可靠性评价要求具有很强的时效性,集成电路芯片固有失效机理的可靠性评价将在工艺开发、建库及工程服务中发挥作用,并有助于推动国内合格生产线认证的开展。

Abstract

The reliability of ULSI/VLSI integrated circuit chips is related to both design and process. In order to make the chip of ULSI/VLSI operate stably during a specific lifetime, it is necessary to evaluate the inherent failure mechanism that affects the reliability of chips. The purpose of the evaluation is to determine the mechanism of technical wear and ensure that the chip has good reliability throughout the product life by improving the design and process processing level. This paper reviews the reliability evaluation standards of inherent failure mechanisms at home and abroad, expounds these inherent mechanisms, summarizes the experiment methods of different inherent failure mechanisms, and puts forward the reliability evaluation requirements of inherent failure mechanisms. The reliability evaluation of failure mechanisms play a role in process development, library construction and engineering services, and will promote the development of domestic qualitied manufacturer certification.

导出引用

章晓文, 周斌, 牛皓, 等. 集成电路固有失效机理的可靠性评价综述[J]. 集成电路与嵌入式系统. 2024, 24(7): 1-11 https://doi.org/10.20193/j.ices2097-4191.2024.07.001

ZHANG Xiaowen, ZHOU Bin, NIU Hao, et al. Review on the reliability evaluation of inherent failure mechanism of integrated circuits[J]. Integrated Circuits and Embedded Systems. 2024, 24(7): 1-11 https://doi.org/10.20193/j.ices2097-4191.2024.07.001

中图分类号： TN386.1

参考文献

列表( 原文顺序 | 文献年度倒序 | 文中引用次数倒序 ) 可视化分析

[1]

章晓文, 恩云飞, 林晓玲, 等. 集成电路可靠性表征结构试验方法:GJB10489-2022[S]. 北京: 总装备部军标出版发行部, 2022.

ZHANG

X W

, EN

Y F

, LIN

X L

, et al. Test methods for the integrated circuits technology characterization vehicle. GJB10489-2022[S]. Beijing: General Equipment Department Military Standard Publishing and Distribution Department, 2022 (in Chinese).

本文引用 [6]

[2]

李锟, 陈裕焜, 秦国林, 等. 合格制造厂认证用半导体集成电路通用规范:GJB7400-2011[S]. 北京: 总装备部军标出版发行部, 2012.

, CHEN

Y K

, QIN

G L

, et al. General specification for semiconductor integrated circuits of qualitied manufacturer certification:GJB7400-2011[S]. Beijing: General Equipment Department Military Standard Publishing and Distribution Department, 2012 (in Chinese).

本文引用 [3]

[3]	张汝京. 纳米集成电路制造工艺[M]. 2版. 北京: 清华大学出版社, 2017:191-207. ZHANG R J. Nanoscale Integrated Circuits—The Manufacturing Process[M]. Second Edition. Beijing: Tsinghua University Press, 2017:191-207 (in Chinese). 本文引用 [2]

[4]	章晓文, 恩云飞. 半导体集成电路的可靠性及评价方法[M]. 北京: 电子工业出版社, 2015:142-193. ZHANG X W, EN Y F. Reliability and evaluation methods of semiconductor integrated circuits[M]. Beijing: Electronics Industry Press, 2015:142-193 (in Chinese). 本文引用 [2]

[5]	Jedec solid state technology association. Foundry Process Qualification Guidelines-Backend of Line: JEP001-1A[S]. USA: Jedec solid state technology association, 2018. 本文引用 [1]

[6]	ZHANG X W, EN Y F. The Reliability Study of 0.13μm CMOS Process[C]// ICRMS 2014,GuangZhou,2014. 本文引用 [1]

[7]	ZHANG X W, EN Y F. The HCI Effect Reliability Evaluation of CMOS Process[C]// EDSSC 2014,Chengdu,2014. 本文引用 [1]

[8]	C Y SU, M ARMSTRONG, L JIANG, et al. Circuit Level Reliability Simulator for Front-End-of Line and Middle-of-Line Time-Dependent Dielectric Breakdown in FinFET Technology[C]// IEEE 36th VLSI Test Symposium, 2018. 本文引用 [2]

[9]	CHANGZE LIU, HYUN-CHUL SAGONG, HYEJIN KIM, et al. Systematical Study of 14nm FinFET Reliability:From Device level stress to Product HTOL[C]// IEEE IRPS, 2015. 本文引用 [1]

[10]	郑敦仁. 元件可靠度[J]. 电子与材料, 2000(8):49-55. ZHENG D R. Component reliability[J]. Electronics and Materials, 2000(8):49-55 (in Chinese). 本文引用 [5]

[11]	D G PIERCE, P G BRUSIUS. Electromigration:A Review[J]. Microelectron. Reliab., 1997, 37(7):1053 -1072. 本文引用 [4]

[12]	American society for testing and materials. Standard Test Method for Estimating Electromigration Median Time-To-Failure and Sigma of Integrated Circuit Metallizations [Metric]:F1260M-96[S]. East Inglewood,ASTM,1996. 本文引用 [1]

[13]	The International Electrotechnical Commission. Semiconductor devices-Constant current electromigration test:IEC 62415-2010[S]. Geneva: The International Electrotechnical Commission, 2010. 本文引用 [3]

[14]	The International Electrotechnical Commission. Semiconductor devices-Hot carrier test on MOS transistors:62416-2010[S]. Geneva: The International Electrotechnical Commission, 2010. 本文引用 [4]

[15]	The International Electrotechnical Commission. Semiconductor devices-Time dependent dielectric breakdown (TDDB) test for gate dielectric films:62416-2007[S]. Geneva: The International Electrotechnical Commission, 2007. 本文引用 [2]

[16]	The International Electrotechnical Commission. Semiconductor devices-Bias-Temperature Stability Test for Metal-Oxide,Semiconductor,Field-Effect Transistors(MOSFET):62373-2006[S]. Geneva: The International Electrotechnical Commission, 2006. 本文引用 [2]

[17]	United States of America Defense and Department. mil-prf-38535L Integrated circuits (microcircuits) manufacturing,general specification for.US:MIL, 2018:12. 本文引用 [1]

[18]	Standard of Electronic Industries Association of Japan. EIAJ ED-4704 Failure mechanism drive reliability test methods for LSIs. Tok: Electronic Industries Association of Japan, 2000:5. 本文引用 [1]

[19]	Jedec solid state technology association. A Procedure for Measuring N-Channel MOSFET Hot Carrier Induced Degradation Under DC Stress:JESD-28A[S]. USAJedec solid state technology association, 2018. 本文引用 [1]

[20]	Jedec solid state technology association. N-Channel MOSFET Hot Carrier Data Analysis:JESD28-1[S]. USA: Jedec solid state technology association, 2018. 本文引用 [1]

[21]	Jedec solid state technology association. A Procedure for Measuring P-Channel MOSFET Hot Carrier Induced Degradation at Maximum Gate current under DC Stress:JESD60[S]. USA: Jedec solid state technology association, 2018. 本文引用 [1]