本文使用敏捷开发技术设计并改进了SM4算法,在Xilinx FPGA平台完成了实现和验证。针对SM4算法关键路径长、吞吐量较低的缺点,将32个寄存器构成的寄存器组插入轮函数计算过程作为缓存区,采用流水线的方式缩短关键路径和优化S盒模块结构,从而大幅提升了工作频率和吞吐量,分别达到340 MHz和1.2 Gbit/s。同时采用新型高级硬件描述语言BSV进行开发,大幅降低了设计复杂度。与采用Verilog的设计相比,在硬件开销差距不大的情况下性能提升了40%,复杂度降低了60%;与较早前方案相比,资源开销降低了70%,性能提升了1倍,具有较高的应用价值。

This article uses agile development technology to design and improve the SM4 algorithm,and completes the implementation and verification on the Xilinx FPGA platform.In view of the shortcomings of the SM4 algorithm featuring long critical path and low throughput,a register group consisting of 32 registers is inserted into the round function calculation process as a cache area,and the pipeline method is used to shorten the critical path and optimize the S-box module structure,thus greatly improving the work efficiency.Frequency and throughput reach 340 MHz and 1.2 Gbit/s,respectively.At the same time,the new high-level hardware description language BSV is used for development,which greatly reduces the design complexity.Compared with the design using Verilog,the performance is 40% higher and the complexity is 60% lower without notable difference in hardware overhead.Compared with the earlier solution,the resource overhead is reduced by 70%,the performance is doubled,and it has higher application value.