针对神经常微分方程网络推理在冯·诺依曼架构中面临“功耗墙”和“存储墙”瓶颈、在传统存内计算架构中因存在大量数/模、模/数转换而产生过多的时间和功耗开销等问题,提出一种基于RRAM的面向神经常微分方程网络的全模拟存内计算架构,能够实现纯模拟数据流的神经常微分方程网络推理。架构仿真工作在Cadence Virtuoso平台上完成,通过该平台对RRAM器件、阵列及其外围电路进行仿真与分析。架构测试工作基于40 nm工艺的RRAM测试平台和差分输入/输出PCB板,完成整个系统的功能验证。结合测试误差对神经常微分方程网络分类任务进行实验与评估,最终证明了该架构的功能性和可靠性,为后续的硬件实现和应用部署奠定了坚实基础。

Neural ordinary differential equation (ODE) network inference in Von Neumann architectures faces problems like the "power wall" and "memory wall". Traditional in-memory computing architectures also suffer from excessive time and power consumption due to numerous digital-to-analog and analog-to-digital conversions. To address these issues, we propose a fully analog compute-in-memory architecture for Neural ODEs based on RRAM to achieve fully analog data flow in network inference. The simulation is completed on the Cadence Virtuoso platform, which includes RRAM device, array, and the peripheral circuits. The test is performed on a 40 nm RRAM test platform and differential input/output PCB, achieving functional verification of the entire system. Experiments and evaluations of the classification tasks of Neural ODEs are conducted with testing errors, ultimately proving the functionality and reliability of the architecture. This lays a solid foundation for subsequent hardware implementation and application deployment.