宇航环境下基于RHBD的SRAM抗双节点翻转研究综述

帅威; 蔡烁; 陈俊伊; 陈俊哲; 梁鑫杰; 黄珠; 魏懋萱

doi:10.20193/j.ices2097-4191.2025.0097

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集成电路与嵌入式系统 ›› 2026, Vol. 26 ›› Issue (3) : 20-33. DOI: 10.20193/j.ices2097-4191.2025.0097

第九届全国大学生集成电路创新创业大赛优秀作品专刊

宇航环境下基于RHBD的SRAM抗双节点翻转研究综述

帅威 ¹ ,
蔡烁 ¹^,^* ,
陈俊伊 ¹ ,
陈俊哲 ¹ ,
梁鑫杰 ² ,
黄珠 ¹ ,
魏懋萱 ³

作者信息 +

A review of RHBD-based SRAM design against double node upsets in space environment

SHUAI Wei ¹ ,
CAI Shuo ¹^,^* ,
CHEN Junyi ¹ ,
CHEN Junzhe ¹ ,
LIANG Xinjie ² ,
HUANG Zhu ¹ ,
WEI Maoxuan ³

Author information +

文章历史 +

摘要

在宇航等高可靠性应用环境中,由辐射引发的多节点翻转已成为影响静态随机存储器稳定性的关键因素。近年来,针对双节点翻转问题,基于辐射加固设计策略的多种抗干扰结构被提出并得到广泛研究,典型的如S8P8N、QUCCE12T、SARP12T、HRLP16T、RH20T、S6P8N与RH14T等。文中系统回顾了现有RHBD型SRAM结构在DNU容错方面的设计理念与关键性能指标,梳理其在可靠性、功耗、面积、访问速度及静态稳定性等方面的优势与局限,并对比分析不同设计策略的适用场景。最后,指出当前RHBD结构在细粒度容错控制与综合性能平衡方面仍面临的挑战,未来设计可在电荷传播路径抑制、反馈机制优化等方向进一步突破。

Abstract

In high-reliability applications such as aerospace, satellite communication, and nuclear control systems, multiple node upsets (MNUs) induced by radiation have become a major threat to the stability of static random access memory (SRAM). In recent years, to address the double node upset (DNU) issue, various radiation-hardened-by-design (RHBD) structures have been proposed and extensively studied, including S8P8N, QUCCE12T, SARP12T, HRLP16T, RH20T, S6P8N, and RH14T.This paper provides a comprehensive review of RHBD-based SRAM designs with a focus on their fault-tolerance mechanisms against DNU events. The key design principles, performance metrics, and trade-offs among reliability, power consumption, area, access time, and static stability are summarized and compared. Finally, the paper points out that existing RHBD structures still face challenges in achieving fine-grained fault tolerance and balanced overall performance. Future development may focus on charge propagation suppression and feedback mechanism optimization to further enhance DNU resilience.

导出引用

帅威, 蔡烁, 陈俊伊, 等. 宇航环境下基于RHBD的SRAM抗双节点翻转研究综述[J]. 集成电路与嵌入式系统. 2026, 26(3): 20-33 https://doi.org/10.20193/j.ices2097-4191.2025.0097

SHUAI Wei, CAI Shuo, CHEN Junyi, et al. A review of RHBD-based SRAM design against double node upsets in space environment[J]. Integrated Circuits and Embedded Systems. 2026, 26(3): 20-33 https://doi.org/10.20193/j.ices2097-4191.2025.0097

中图分类号： TN47 (大规模集成电路、超大规模集成电路)

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摘要

神经网络是人工智能的代表性算法,然而其庞大的参数量对其在边缘端的硬件部署提出了新的挑战。在边缘端,一方面,为了应用的灵活性,要求计算硬件能够通过模型参数的微调来实现网络在任务间的迁移;另一方面,为了计算能效和性能,需要实现大容量的片上存储以减少片外访存开销。近期提出的ROM-SRAM混合存内计算架构是在成熟CMOS工艺下很有潜力的一种方案。得益于高密度ROM存内计算,神经网络的大部分权重可以部署在片内而不依赖片外访存;与此同时,SRAM存内计算可以为基于高密度ROM的边缘端存内计算提供灵活性。为了扩展ROM-SRAM混合存内计算架构设计和应用的空间,需要进一步提高ROM存内计算的密度以支持更大的网络,并探索通过少量SRAM存内计算获得更大灵活性的方案。文中介绍了几种常见的提升ROM存内计算密度的方法,以及基于ROM-SRAM混合存内计算架构的神经网络微调以提升灵活性的方法,并讨论了超大规模神经网络的部署方案和长序列大语言模型中遇到的动态矩阵乘瓶颈的解决方案,展望了ROM-SRAM混合存内计算架构广阔的设计空间和应用前景。

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本文引用 [1] 摘要

With the rapid advancement of cutting-edge technologies such as artificial intelligence and quantum computing, the demand for high-performance computing chips continues to increase. However, traditional von Neumann architectures are increasingly constrained by the memory wall and power wall, making it difficult to meet the computing demands of data-intensive applications. Cryogenic in-memory computing combines the superior electrical properties of cryogenic CMOS devices with the high bandwidth and low latency advantages of in-memory computing architectures, providing a new solution to overcome computing bottlenecks. This review summarizes the key characteristics of CMOS devices and various memory media at cryogenic temperatures, systematically reviews representative architectures, key implementations, and performance metrics of cryogenic in-memory computing in the fields of artificial intelligence and quantum computing. Moreover, this review analyzes the challenges and development trends at the levels of device technology, circuit systems, and EDA tools.

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