设计了一种用于高速SerDes接收机的模拟前端电路,针对不同信道损耗,采用Gm-TIA架构实现了连续可调的连续时间线性均衡器(CTLE)和可变增益放大器(VGA)。CTLE在奈奎斯特频率处提供2.2~12.5 dB可调峰值增益,VGA增益范围为-8~3.5 dB,可灵活适配多种信道特性。电路通过互补跨导结构实现电流复用,提升跨导与能效;利用T型电感与ESD、PAD等寄生参数协同设计,实现宽带阻抗匹配;采用电感峰化与可调MOS电阻以拓展带宽、实现增益连续调节。基于65 nm CMOS工艺完成设计,后仿真结果表明,该前端在25 GHz奈奎斯特频率处可实现1.1~11.5 dB峰值增益,支持100 Gb/s PAM4信号传输,在1.2 V电源电压下功耗为12.83 mW。
This paper presents an analog front-end circuit for high-speed SerDes receivers, designed to address varying channel losses. Utilizing a transconductance-transimpedance (Gm-TIA) architecture, the circuit implements a continuous-time linear equalizer (CTLE) with a tunable peaking gain of 2.2~12.5 dB at the Nyquist frequency and a variable gain amplifier (VGA) with a gain range of -8~3.5 dB, offering flexibility for different channel characteristics. A complementary transconductance stage is employed to achieve current reuse, enhancing transconductance and power efficiency. A T-coil structure is designed to achieve broadband impedance matching, considering parasitics from ESD, pads, and AC-coupling. Inductive peaking and tunable MOS resistors are adopted to extend bandwidth and enable continuous gain tuning. Fabricated in a 65 nm CMOS process, post-layout simulations show that the front-end achieves a peaking gain of 1.1~11.5 dB at 25 GHz Nyquist frequency, supports 100 Gb/s PAM4 signal transmission, and consumes 12.83 mW under a 1.2 V supply.