基于耦合峰化电感的低噪声高速串行接口接收机

宋雨霏; 黄庆杰; 田源

doi:10.20193/j.ices2097-4191.2025.0112

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集成电路与嵌入式系统 ›› 2026, Vol. 26 ›› Issue (3) : 54-63. DOI: 10.20193/j.ices2097-4191.2025.0112

第九届全国大学生集成电路创新创业大赛优秀作品专刊

基于耦合峰化电感的低噪声高速串行接口接收机

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Low-noise high-speed serial interface receiver based on coupled peaked inductance

Author information +

文章历史 +

摘要

基于TSMC 65 nm CMOS工艺设计了一款适用于100 Gb/s PAM-4信号的接收机AFE。采用CTLE+VGA+TIA结构,CTLE负责补偿信道损耗,VGA+TIA实现增益控制。CTLE部分结合共源共栅结构、负电容补偿及可调低通滤波技术,在奈奎斯特频率(25 GHz)处实现了2.7~18 dB的补偿范围。VGA与基于反相器的跨阻放大器(TIA)级联,通过4位DAC实现增益以1 dB步进在-3~12 dB范围内精确可调。连续时间线性均衡器(CTLE)及可变增益放大器(VGA)模块输出部分创新性地采用反向耦合电感峰化技术,以拓展带宽、提升增益并优化噪声。同时,TIA采用峰化电感带宽拓展及低阻抗路径噪声优化技术,进一步将系统1 dB带宽拓展至42.8 GHz,同时优化了噪声。此外,提出基于g_m-boosting的级间磁反馈技术,在VGA+TIA级间形成三耦合电感结构,有效提升了整体增益。版图核心面积为0.175 mm²,后仿真结果表明,在补偿5/10/15 dB@25 GHz信道损耗时,整体功耗低于18.7 mW,均方根噪声不超过1.08 mVrms,且能成功开启原本闭合的眼图,各项指标均达到或优于设计目标。

Abstract

This paper presents the design of a receiver AFE suitable for 100 Gb/s PAM-4 signals based on TSMC 65 nm CMOS technology. Employing a CTLE+VGA+TIA architecture, the CTLE compensates for channel loss while the VGA+TIA provides gain control. The CTLE section, incorporating a cascode structure, negative capacitance compensation, and tunable low-pass filtering, achieves a tunable gain range of 2.7 dB to 18 dB at the Nyquist frequency (25 GHz). The VGA, cascaded with an inverter-based transimpedance amplifier (TIA), enables precise gain adjustment in 1 dB steps from -3 dB to 12 dB through a 4-bit DAC. The continuous-time linear equalizer (CTLE) and variable gain amplifier (VGA) modules innovatively implement reverse-coupled inductive peaking technology to enhance bandwidth, improve gain, and optimize noise. Simultaneously, the TIA employs peaking inductor bandwidth extension and low-impedance path noise optimization techniques, extending the system's 1 dB bandwidth to 42.8 GHz while further optimizing noise. Additionally, this paper introduces a g_m-boosting-based interstage magnetic feedback technique, forming a triple-coupled inductor structure between the VGA and TIA stages, effectively enhancing overall gain. The core layout area measures 0.175 mm², and post-simulation results demonstrate that when compensating for 5/10/15 dB@25 GHz channel losses, the total power consumption remains below 18.7 mW, with root mean square noise not exceeding 1.08 mVrms. The system successfully opens previously closed eye diagrams, with all performance metrics meeting or exceeding design specifications.

导出引用

宋雨霏, 黄庆杰, 田源. 基于耦合峰化电感的低噪声高速串行接口接收机[J]. 集成电路与嵌入式系统. 2026, 26(3): 54-63 https://doi.org/10.20193/j.ices2097-4191.2025.0112

SONG Yufei, HUANG Qingjie, TIAN Yuan. Low-noise high-speed serial interface receiver based on coupled peaked inductance[J]. Integrated Circuits and Embedded Systems. 2026, 26(3): 54-63 https://doi.org/10.20193/j.ices2097-4191.2025.0112

中图分类号： TP872 (远距离控制和信号、远距离控制和信号系统)

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