随着集成电路特征尺寸不断缩小,天线效应对芯片可靠性的影响日益凸显。层分配作为物理设计的关键环节,需将二维布线结果分配到多层三维空间,但不合理的层分配会导致导线形成过长天线,积累过多电荷而击穿栅极。然而,现有研究主要聚焦于时延和通孔优化,并未充分考虑天线效应,且先进制程中广泛应用的非默认规则线技术因线宽更大,会加剧天线效应。为此,提出一种先进制程下考虑天线效应的层分配算法,包含四项核心策略:天线代价感知的动态规划策略,在初始阶段即减少天线违规;高层优先的导线段重分配策略,精确控制高层天线面积增长;时序感知的非默认规则线替换策略,在控制时延影响的前提下修复违规;网格边资源协商策略,通过跨线网协同释放布线资源。实验结果表明,算法在保持时延和通孔数优良性能的同时,显著减少了天线违规线网和引脚数量。

As integrated circuit feature sizes continue to shrink, the antenna effect increasingly impacts chip reliability. Layer assignment, a critical step in physical design, allocates 2D routing segments into a multi-layer 3D space. Improper assignment can cause wires to form excessively long antennas that accumulate charge and damage gates. However, existing research primarily focuses on delay and via optimization without adequately considering antenna effects. Moreover, the widely adopted non-default-rule (NDR) wire technology in advanced nodes exacerbates antenna effects due to larger wire widths. This paper proposes an antenna-aware layer assignment algorithm for advanced technology nodes comprising four core strategies. An antenna-cost-aware dynamic programming strategy that reduces violations during initialization. A high-layer-priority segment reassignment strategy that precisely controls antenna area growth. A timing-aware NDR replacement strategy that fixes violations while limiting delay impact. A g-edge resource negotiation strategy that releases routing resources through cross-net coordination. The experimental results demonstrate that the proposed algorithm significantly reduces antenna-violating nets and pins while maintaining excellent delay and via count performance.