随着片上系统(SoC)设计日益追求高性能与高可靠性,以满足各种AI应用场景处理海量数据的严苛要求。奇偶校验机制被广泛引入电路设计中以增强SoC数据传输的可靠性。然而,在宽位宽传输数据场景下,传统的奇偶校验电路设计面临校验复杂度高、译码延时大等问题,制约了SoC整体性能,如系统主时钟频率和数据访存带宽。针对这一技术难题,创新性地提出了一种面向SoC内存的AXI总线多级流水线奇偶校验电路设计方法。该设计通过流水线架构对校验过程进行分级优化,显著减小了数据通路中关键路径的延时。实验结果表明,在电路总面积增加0.47%和功耗上升0.24%的微小代价下,所提出设计方法实现了数据读/写通路关键路径的时序优化,将AXI总线写数据和读数据通道路径最大延时分别降低了18.62%和25.60%,有效提升了SoC整体性能与可靠性。

As SoC architectures evolve to meet the computational intensity of diverse AI applications, the pursuit of high-performance throughput must be balanced with uncompromising reliability. Consequently, parity check mechanisms have emerged as a cornerstone of modern circuit design, essential for safeguarding the integrity of massive data movement within the SoC fabric. However, in wide-bit-width data transmission scenarios, traditional parity check circuit designs face challenges such as high verification complexity and significant decoding latency, which in turn constrain the overall performance of SoCs, including system master clock frequency and data access bandwidth. To address this technical challenge, this paper innovatively proposes a multi-stage pipelined parity check circuit design method for the AXI bus in SoC memory. This design employs a pipelined architecture to optimize the verification process in stages, significantly reducing the critical path delay in the data pathway. The experiment results demonstrate that, at a minimal cost of a 0.47% increase in total circuit area and a 0.24% rise in power consumption, the proposed design method achieves timing optimization of the date read/write bus critical path, reducing the maximum delay of the AXI bus write and read data circuit paths by 18.62% and by 25.60% respectively, effectively enhancing the overall performance and reliability of the SoC.