介绍了一款采用55 nm CMOS工艺制造的10位、1 GSa/s、八通道时间交织逐次逼近寄存器(TI-SAR)ADC的设计及系统性宽温表征。该TI-SAR ADC由8个异步 SAR 子 ADC 构成,并集成局部参考缓冲、基于SRAM和SPI的数据传输、片外失配估计以及片上可调采样延时校正。采用低频和近奈奎斯特频率输入信号,在宽温范围内对芯片进行测试,并从有效位数(ENOB)、信噪比(SNR)、谐波失真以及与时间交织相关的残余频谱分量等方面分析测量结果。测试结果表明,该ADC在整个测试温度范围内可以实现6.37~6.79位的有效位数(ENOB);对于49.987 8 MHz和450.012 2 MHz输入信号,温度由-25 ℃ 升高至 95 ℃ 时,SNR分别下降1.35 dB和1.71 dB,整体功耗为22.36 mW。进一步利用完整的高温校准记录验证了在最严苛测试条件下时序校正链路仍能正常工作。归一化误差功率分析结果表明,高温性能退化主要源于残余背景误差增加,而非校准后时间交织失配恶化,为宽温 TI-ADC 的鲁棒性评估和残余误差诊断提供了依据。

This paper presents the design and extensive wide-temperature characterization of a 10-bit, 1 GSa/s, 8-channel time-interleaved successive approximation register (TI-SAR) ADC fabricated in a 55 nm CMOS process. The converter employs eight asynchronous SAR sub-ADCs and integrates local reference buffering, SRAM and SPI-based data transfer, off-chip mismatch estimation, and on-chip adjustable sampling delay correction. The prototype is evaluated over a wide temperature range using low-frequency and near-Nyquist input tones. The measurement results are analyzed in terms of effective number of bits (ENOB), signal-to-noise ratio (SNR), harmonic distortion, and residual spectral components associated with interleaving. Measurement results show that the ADC achieves an ENOB of 6.37~6.79 bits over the measured temperature range. As the temperature increases from -25 ℃ to 95 ℃, the SNR decreases by 1.35 dB and 1.71 dB for 49.987 8 MHz and 450.012 2 MHz input tones, respectively, with a total power consumption of 22.36 mW. A complete high-temperature calibration record is further used to verify that the timing correction path remains functional under the most severe measured condition. Normalized error-power analysis shows that the high-temperature degradation is mainly associated with increased residual background error rather than deterioration of calibrated interleaving mismatch. These results support wide-temperature robustness evaluation and residual-error diagnosis of TI-ADCs.