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基于条件自回归Transformer的NBTI老化轨迹预测
秦豪斌, 王哲锐, 单书珊, 方利泉, 郑飞君
集成电路与嵌入式系统 ›› 2026, Vol. 26 ›› Issue (11) : 14-25.
PDF(12784 KB)
PDF(12784 KB)
基于条件自回归Transformer的NBTI老化轨迹预测
Conditional autoregressive Transformer for NBTI aging trajectory prediction
随着CMOS工艺节点持续微缩,诸如负偏压温度不稳定性(NBTI)等老化效应日益显著,并已成为电路可靠性的关键影响因素,对集成电路因老化引起的性能退化进行精确预测,有助于降低现场失效的风险。一种具有前景的预测范式是持续采集芯片运行条件,包括供电电压、温度、信号占空比以及部分性能退化信息,据此构建机器学习模型,并利用历史退化观测数据预测未来的退化趋势。这一能力与硅生命周期管理(SLM)的目标高度契合,后者旨在监测、分析并优化芯片在整个运行寿命期间的性能。文中提出条件自回归Transformer(CAT),一种仅含解码器的序列预测模型,该模型以芯片运行环境及历史退化轨迹为条件,预测未来时间范围内的退化轨迹。CAT利用因果注意力机制捕获NBTI老化动态中固有的时间依赖性,从而基于部分传感器数据实现多步外推。实验结果表明,CAT能够实现精确的退化预测,为先进CMOS工艺下基于SLM的可靠性管理提供了一种实用解决方案。
As CMOS technology nodes continue to scale down, aging effects such as Negative Bias Temperature Instability (NBTI) have become increasingly significant and have emerged as critical factors affecting circuit reliability. Accurate prediction of the aging-induced performance degradation in integrated circuits can mitigate the risk of in-field failures. A promising prediction paradigm involves the continuous collection of chip operating conditions, including supply voltage, temperature, signal duty cycle, and partial performance-degradation information, and constructing a machine-learning model that uses past degradation observations to forecast future degradation trends. Such a capability aligns closely with the objectives of Silicon Lifecycle Management (SLM), which seeks to monitor, analyze, and optimize chip performance throughout its operational lifetime. In this paper, we propose the Conditional Autoregressive Transformer (CAT), a decoder-only sequential prediction model that, conditioned on chip operating conditions and historical degradation traces, predicts the degradation trajectory over a future time horizon. CAT leverages causal attention mechanisms to capture the temporal dependencies inherent in NBTI aging dynamics, enabling multi-step extrapolation from partial sensor data. Experimental results demonstrate that CAT achieves accurate degradation forecasting, offering a practical solution for SLM-driven reliability management in advanced CMOS technologies.
NBTI / 电路可靠性 / 老化轨迹预测 / 芯片生命周期管理 / 序列预测 / 仅含解码器的Transformer
NBTI / circuit reliability / aging trajectory prediction / Silicon Lifecycle Management (SLM) / sequential prediction / decoder-only Transformer
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As CMOS technology continues to scale down, the aging effect—known as negative bias temperature instability (NBTI)—has become increasingly prominent, gradually emerging as a key factor affecting device reliability. Accurate aging-aware static timing analysis (STA) at the early design phase is critical for establishing appropriate timing margins to ensure circuit reliability throughout the chip lifecycle. However, traditional aging-aware timing analysis methods, typically based on Simulation Program with Integrated Circuit Emphasis (SPICE) simulations or aging-aware timing libraries, struggle to balance prediction accuracy with computational cost. In this paper, we propose a multi-view graph learning framework for path-level aging-aware timing prediction, which combines the strengths of the spatial–temporal Transformer network (STTN) and graph attention network (GAT) models to extract the aging timing features of paths from both timing-sensitive and workload-sensitive perspectives. Experimental results demonstrate that our proposed framework achieves an average MAPE score of 3.96% and reduces the average MAPE by 5.8 times compared to FFNN and 2.2 times compared to PNA, while maintaining acceptable increases in processing time.
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