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PDF(14780 KB)
PDF(14780 KB)
基于晶圆级测试的硅光芯片光纤耦合技术研究
Wafer-level testing-based fiber coupling technology for silicon photonic integrated circuit
随着人工智能大模型、超大规模数据中心和高性能计算的快速发展,系统互连正向更高速率、更高带宽密度和更低功耗方向演进。硅光子集成芯片(Silicon Photonic Integrated Circuit,SiPh PIC)凭借CMOS工艺兼容、高集成度和低功耗等优势,已成为高速光互连和光电共封装(Co-Packaged Optics,CPO)光引擎的重要技术基础。然而,标准单模光纤与硅波导之间存在显著的模场尺寸失配,同时端面反射、折射率不连续和对准误差也会引入额外损耗,使高效率、可重复的光纤耦合成为晶圆级测试、封装集成及CPO光引擎验证中的关键挑战。论文围绕晶圆级硅光PIC光纤耦合技术展开综述。首先,介绍自动化耦合系统的组成、测试流程及误差来源;随后,重点分析光栅耦合和边缘耦合的工作原理、典型结构及性能特点;接着,进一步讨论单模光纤、透镜光纤、光纤阵列和新型光探针等耦合器件,以及主动对准、被动对准和自动化耦合控制算法;最后,对光纤耦合技术向低损耗、高容差、多通道并行、自动化寻优和数据闭环方向的发展趋势进行展望。该研究可为硅光PIC晶圆级测试平台构建、光纤阵列封装和CPO光引擎集成验证提供重要参考。
With the rapid development of large-scale artificial intelligence models, hyperscale data centers, and high-performance computing, system interconnects are evolving toward higher data rates, higher bandwidth density, and lower power consumption. Silicon photonic integrated circuits (SiPh PICs), benefiting from CMOS-compatible fabrication, high integration density, and low power consumption, have become an important technology platform for high-speed optical interconnects and co-packaged optics (CPO) optical engines. However, efficient and repeatable fiber-to-chip coupling remains a key challenge in wafer-level testing, packaging integration, and CPO optical engine verification. This is mainly attributed to the significant mode-field mismatch between standard single-mode fibers and silicon waveguides. In addition, facet reflection, refractive-index discontinuity, and alignment errors may introduce extra optical loss and affect measurement accuracy. This paper reviews wafer-level fiber coupling technologies for SiPh PICs. First, the architecture, testing workflow, and main error sources of automated coupling systems are introduced. Then, grating coupling and edge coupling are analyzed in terms of operating principles, typical structures, and performance characteristics. Furthermore, coupling devices such as single-mode fibers, lensed fibers, fiber arrays, and emerging optical probes are discussed, together with active alignment, passive alignment, and automated coupling control algorithms. Finally, future trends are summarized, including low-loss coupling, high alignment tolerance, multi-channel parallel testing, automated optimization, and data-driven feedback. This review provides a reference for wafer-level SiPh PIC testing platforms, fiber-array packaging, and CPO optical engine integration and verification.
硅光芯片 / 晶圆级测试 / 光纤耦合 / 有源对准 / 无源对准 / 边缘耦合 / 光栅耦合
silicon photonic integrated circuits / wafer-level testing / fiber coupling / active alignment / passive alignment / edge coupling / grating coupling
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Silicon photonics research can be dated back to the 1980s. However, the previous decade has witnessed an explosive growth in the field. Silicon photonics is a disruptive technology that is poised to revolutionize a number of application areas, for example, data centers, high-performance computing and sensing. The key driving force behind silicon photonics is the ability to use CMOS-like fabrication resulting in high-volume production at low cost. This is a key enabling factor for bringing photonics to a range of technology areas where the costs of implementation using traditional photonic elements such as those used for the telecommunications industry would be prohibitive. Silicon does however have a number of shortcomings as a photonic material. In its basic form it is not an ideal material in which to produce light sources, optical modulators or photodetectors for example. A wealth of research effort from both academia and industry in recent years has fueled the demonstration of multiple solutions to these and other problems, and as time progresses new approaches are increasingly being conceived. It is clear that silicon photonics has a bright future. However, with a growing number of approaches available, what will the silicon photonic integrated circuit of the future look like? This roadmap on silicon photonics delves into the different technology and application areas of the field giving an insight into the state-of-the-art as well as current and future challenges faced by researchers worldwide. Contributions authored by experts from both industry and academia provide an overview and outlook for the silicon waveguide platform, optical sources, optical modulators, photodetectors, integration approaches, packaging, applications of silicon photonics and approaches required to satisfy applications at mid-infrared wavelengths. Advances in science and technology required to meet challenges faced by the field in each of these areas are also addressed together with predictions of where the field is destined to reach.
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Over the last 20 years, silicon photonics has revolutionized the field of integrated optics, providing a novel and powerful platform to build mass-producible optical circuits. One of the most attractive aspects of silicon photonics is its ability to provide extremely small optical components, whose typical dimensions are an order of magnitude smaller than those of optical fiber devices. This dimension difference makes the design of fiber-to-chip interfaces challenging and, over the years, has stimulated considerable technical and research efforts in the field. Fiber-to-silicon photonic chip interfaces can be broadly divided into two principle categories: in-plane and out-of-plane couplers. Devices falling into the first category typically offer relatively high coupling efficiency, broad coupling bandwidth (in wavelength), and low polarization dependence but require relatively complex fabrication and assembly procedures that are not directly compatible with wafer-scale testing. Conversely, out-of-plane coupling devices offer lower efficiency, narrower bandwidth, and are usually polarization dependent. However, they are often more compatible with high-volume fabrication and packaging processes and allow for on-wafer access to any part of the optical circuit. In this paper, we review the current state-of-the-art of optical couplers for photonic integrated circuits, aiming to give to the reader a comprehensive and broad view of the field, identifying advantages and disadvantages of each solution. As fiber-to-chip couplers are inherently related to packaging technologies and the co-design of optical packages has become essential, we also review the main solutions currently used to package and assemble optical fibers with silicon-photonic integrated circuits. Published by Chinese Laser Press under the terms of the Creative Commons Attribution 4.0 License.
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Silicon photonics has drawn increasing attention in the past few decades and is a promising key technology for future daily applications due to its various merits including ultra-low cost, high integration density owing to the high refractive index of silicon, and compatibility with current semiconductor fabrication process. Optical interconnects is an important issue in silicon photonic integrated circuits for transmitting light, and fiber-to-chip optical interconnects is vital in application scenarios such as data centers and optical transmission systems. There are mainly two categories of fiber-to-chip optical coupling: off-plane coupling and in-plane coupling. Grating couplers work under the former category, while edge couplers function as in-plane coupling. In this paper, we mainly focus on edge couplers in silicon photonic integrated circuits. We deliver an introduction to the research background, operation mechanisms, and design principles of silicon photonic edge couplers. The state-of-the-art of edge couplers is reviewed according to the different structural configurations of the device, while identifying the performance, fabrication feasibility, and applications. In addition, a brief comparison between edge couplers and grating couplers is conducted. Packaging issues are also discussed, and several prospective techniques for further improvements of edge couplers are proposed.
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Silicon photonics is an enabling technology that provides integrated photonic devices and systems with low-cost mass manufacturing capability. It has attracted increasing attention in both academia and industry in recent years, not only for its applications in communications, but also in sensing. One important issue of silicon photonics that comes with its high integration density is an interface between its high-performance integrated waveguide devices and optical fibers or free-space optics. Surface grating coupler is a preferred candidate that provides flexibility for circuit design and reduces effort for both fabrication and alignment. In the past decades, considerable research efforts have been made on in-plane grating couplers to address their insufficiency in coupling efficiency, wavelength sensitivity and polarization sensitivity compared with out-of-plane edge-coupling. Apart from improved performances, new functionalities are also on the horizon for grating couplers. In this paper, we review the current research progresses made on grating couplers, starting from their fundamental theories and concepts. Then, we conclude various methods to improve their performance, including coupling efficiency, polarization and wavelength sensitivity. Finally, we discuss some emerging research topics on grating couplers, as well as practical issues such as testing, packaging and promising applications.
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Wafer-level probing of photonic integrated circuits is key to reliable process control and efficient performance assessment in advanced production workflows. In recent years, optical probing of surface-coupled devices such as vertical-cavity lasers, top-illuminated photodiodes, or silicon photonic circuits with surface-emitting grating couplers has seen great progress. In contrast to that, wafer-level probing of edge-emitting devices with hard-to-access vertical facets at the sidewalls of deep-etched dicing trenches still represents a major challenge. In this paper, we address this challenge by introducing a novel concept of optical probes based on 3D-printed freeform coupling elements that fit into deep-etched dicing trenches on the wafer surface. Exploiting the design freedom and the precision of two-photon laser lithography, the coupling elements can be adapted to a wide variety of mode-field sizes. We experimentally demonstrate the viability of the approach by coupling light to edge-emitting waveguides on different integration platforms such as silicon photonics (SiP), silicon nitride (TriPleX), and indium phosphide (InP). Achieving losses down to 1.9 dB per coupling interface, we believe that 3D-printed coupling elements represent a key step towards highly reproducible wafer-level testing of edge-coupled photonic integrated circuits.
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We propose and demonstrate an efficient coupler for compact mode conversion between a fiber and a submicrometer waveguide. The coupler is composed of high-index-contrast materials and is based on a short taper with a nanometer-sized tip. We show that the micrometer-long silicon-on-insulator-based nanotaper coupler is able to efficiently convert both the mode field profile and the effective index, with a total length as short as 40 microm. We measure an enhancement of the coupling efficiency between an optical fiber and a waveguide by 1 order of magnitude due to the coupler.
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Fiber-chip edge couplers are extensively used in integrated optics for coupling of light between planar waveguide circuits and optical fibers. In this work, we report on a new fiber-chip edge coupler concept with large mode size for silicon photonic wire waveguides. The coupler allows direct coupling with conventional cleaved optical fibers with large mode size while circumventing the need for lensed fibers. The coupler is designed for 220 nm silicon-on-insulator (SOI) platform. It exhibits an overall coupling efficiency exceeding 90%, as independently confirmed by 3D Finite-Difference Time-Domain (FDTD) and fully vectorial 3D Eigenmode Expansion (EME) calculations. We present two specific coupler designs, namely for a high numerical aperture single mode optical fiber with 6 µm mode field diameter (MFD) and a standard SMF-28 fiber with 10.4 µm MFD. An important advantage of our coupler concept is the ability to expand the mode at the chip edge without leading to high substrate leakage losses through buried oxide (BOX), which in our design is set to 3 µm. This remarkable feature is achieved by implementing in the SiO upper cladding thin high-index SiN layers. The SiN layers increase the effective refractive index of the upper cladding near the facet. The index is controlled along the taper by subwavelength refractive index engineering to facilitate adiabatic mode transformation to the silicon wire waveguide while the Si-wire waveguide is inversely tapered along the coupler. The mode overlap optimization at the chip facet is carried out with a full vectorial mode solver. The mode transformation along the coupler is studied using 3D-FDTD simulations and with fully-vectorial 3D-EME calculations. The couplers are optimized for operating with transverse electric (TE) polarization and the operating wavelength is centered at 1.55 µm.
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This paper has proposed an automatic precise alignment coupling algorithm of planar optical waveguide devices based on polynomial fitting, and the experiment shows that for 1 × 8 planar optical waveguide splitter, the time it takes for alignment is within 2.5 min and for 1 × 16 planar optical waveguide splitter, the required time is within 3 min. For 1 × 8 planar optical waveguide splitter, many repeated experiments can guarantee that the insertion loss of the device channels is less than 10.5 dB, with the maximum uniformity of 0.67 dB; for 1 × 16 planar optical waveguide splitter, many repeated experiments can guarantee that the insertion loss of the device channels is less than 13.7 dB, with the maximum uniformity of 0.66 dB. The alignment velocity, precision, and reliability of this algorithm are all greatly increased.
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