随着CMOS工艺持续微缩至55 nm节点,栅氧化层厚度减薄,经时介质击穿(TDDB)将成为制约芯片可靠性的关键失效机制。在栅氧化层TDDB寿命预测中,E模型、1/E模型、幂律模型和$\sqrt{\mathrm{E}}$模型的适用性长期存在争议,不同模型外推结果差异可达几个数量级,直接影响芯片寿命评估的准确性。基于某55 nm工艺栅氧化层TDDB加速寿命测试数据,系统比较了4种主流加速模型在不同应力电压区间(高压区2.7~2.85 V与低压区2.55~2.7 V)的拟合度与外推一致性。计算发现,4种模型均能较好地拟合各自测试数据,但模型适用性呈现显著的电压区间依赖性:高压区E模型拟合度最高R²=0.996 6,1/E模型最低R²=0.994 5;低压区1/E模型拟合度最高R²=0.991,E模型最低R²=0.987 9。幂律模型和$\sqrt{\mathrm{E}}$模型在两个区间均表现居中。测试结果表明,单一模型无法覆盖全电压范围,模型选取应基于应力条件与实际工作电压的相对关系。结合渗流理论、热化学模型与阳极空穴注入模型的理论框架,揭示了不同模型的物理适用边界,并基于高压区最优模型外推得到该55 nm栅氧化层在正常工作电压下的特征寿命。研究结果为先进工艺节点TDDB寿命评估模型选取提供了实验依据,对芯片可靠性设计具有工程指导意义。

As CMOS technology scales to the 55 nm node, the concomitant thinning of the gate oxide has made Time-Dependent Dielectric Breakdown (TDDB) a key mechanism limiting chip reliability. The appropriate model for gate oxide TDDB lifetime projection—whether the E-model, 1/E-model, Power-law model, or $\sqrt{\mathrm{E}}$-model—remains a contentious issue, as extrapolations can differ by several orders of magnitude, thereby compromising the accuracy of lifetime assessments. This study systematically evaluates these four mainstream acceleration models using TDDB data from a 55nm process, comparing their goodness-of-fit across distinct stress regimes: a high-voltage region (2.7~2.85 V) and a low-voltage region (2.55~2.7 V). Our analysis reveals that while all models provide a reasonable fit to their respective data, their applicability is strongly dependent on the voltage regime. The E-model provides the optimal fit in the high-voltage region (R²=0.996 6), where the 1/E-model performs poorly (R²=0.994 5). In contrast, the 1/E-model demonstrates the highest fidelity in the low-voltage region (R²=0.991), where the E-model is least suitable (R²=0.987 9). The Power-law and $\sqrt{\mathrm{E}}$ models exhibit intermediate performance in both regimes. These findings indicate that no single model is universally applicable, instead, model selection must be based on the relationship between the stress conditions and the intended operating voltage. By contextualizing these results within the frameworks of percolation theory, the thermochemical model, and the anode hole injection model, this paper reveals the physical applicability boundaries of each model. Finally, leveraging the optimal model from the high-stress data, we extrapolate the characteristic lifetime of the 55 nm gate oxide at its nominal operating voltage. These research findings provide critical experimental evidence to guide model selection for TDDB lifetime assessment in advanced process nodes and hold significant practical value for robust reliability engineering.