基于ECC症候信息的3D存储die-to-die互连簇状缺陷诊断方法

蒋皓辰, 苏菲

集成电路与嵌入式系统 ›› 2026, Vol. 26 ›› Issue (11) : 26-33.

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集成电路与嵌入式系统 ›› 2026, Vol. 26 ›› Issue (11) : 26-33. DOI: 10.20193/j.ices2097-4191.2026.0087
HIPI ICTS 2026 集成电路测试技术专刊

基于ECC症候信息的3D存储die-to-die互连簇状缺陷诊断方法

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A 3D storage die-to-die interconnect cluster defect diagnosis method based on ECC syndrome information

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摘要

在三维存储系统中,die-to-die互连结构的簇状缺陷是影响系统可靠性的关键因素之一。针对该问题,提出了一种基于片上纠错码(OD-ECC)时空错误信息的实时诊断方法。该方法利用连续多次数据读取中的错误位置信息识别故障模式,并创新性地引入ECC症候(syndrome)作为补充判据,有效区分簇状缺陷导致的固定型故障与随机软错误。建立了die-to-die互连阵列与簇状缺陷的数学模型,推导了不同判断阈值下召回率(Recall)与精确率(Precision)的解析表达式,并搭建了蒙特卡洛仿真平台进行验证。仿真结果表明,在随机错误概率p=10-4、连续读取次数k=12的条件下,所提方法对1×2与2×2 簇状缺陷的召回率分别达98.97%和96.24%,精确率分别为 99.74%和99.16%,显著优于仅利用位置信息的基础诊断方法。所提方法以小幅精度损失为代价,大幅提升了簇状缺陷的检测能力,为三维存储系统可靠性设计提供了有效支撑。

Abstract

Clustering defects in die-to-die interconnect architectures of three-dimensional storage systems constitute one of the critical factors affecting system reliability. To address this challenge, this paper proposes a real-time diagnostic method based on spatio-temporal error information from on-chip error-correcting codes (OD-ECC). The proposed method leverages error location information from multiple consecutive data reads to identify fault patterns, and innovatively incorporates ECC syndrome as an additional criterion to effectively distinguish between fixed faults induced by clustering defects and random soft errors. In this work, we establish a mathematical model for die-to-die interconnect arrays and clustering defects, derive analytical expressions for recall and precision under varying decision thresholds, and construct a Monte Carlo simulation platform for verification. Simulation results demonstrate that, under conditions of a random error probability p=10-4 and k = 12 consecutive reads, the proposed method achieves recall rates of 98.97% and 96.24% for 1×2 and 2×2 clustering defects, respectively, with precision rates of 99.74% and 99.16%, respectively—significantly outperforming baseline diagnostic methods that rely solely on location information. By incurring only a marginal loss in accuracy, this approach substantially enhances the detection capability for clustering defects, thereby providing robust support for the reliability design of three-dimensional storage systems.

关键词

三维存储 / die-to-die互连 / 簇状缺陷 / 纠错码(ECC) / 症候 / 故障诊断

Key words

3D storage / die-to-die interconnect / cluster defects / error-correcting codes (ECC) / syndrome / fault diagnosis

引用本文

导出引用
蒋皓辰, 苏菲. 基于ECC症候信息的3D存储die-to-die互连簇状缺陷诊断方法[J]. 集成电路与嵌入式系统. 2026, 26(11): 26-33 https://doi.org/10.20193/j.ices2097-4191.2026.0087
Jiang Haochen, Su Fei. A 3D storage die-to-die interconnect cluster defect diagnosis method based on ECC syndrome information[J]. Integrated Circuits and Embedded Systems. 2026, 26(11): 26-33 https://doi.org/10.20193/j.ices2097-4191.2026.0087
中图分类号: TP306+.3 (故障诊断与排除)   

参考文献

[1]
K S Choi, et al. A three dimensional DRAM(3D DRAM) technology for the next decades[C]// IEEE Symp VLSI Technol. Circuits, 2024:1-2.
[2]
Gao M Y, Pu J, Yang X, et al. TETRIS:Scalable and efficient neural network acceleration with 3D memory[C]// Proc. 22nd Int. Conf. Architectural Support Program.Lang. Oper. Syst., 2017:751-764.
[3]
S Moreau. Review-Hybrid bonding-based interconnects:A status on the last robustness and reliability achievements[J]. ECS J. Solid State Sci. Technol., 2022, 11(2):024001.
[4]
S Jung, et al. 3D integrated process and hybrid bonding of high bandwidth memory (HBM)[J]. Electron. Mater. Lett., 2025, 21(4):395-419.
[5]
H Lim, S Seo, et al. A low-cost concurrent TSV test architecture with lossless test output compression scheme[J]. PLoS ONE, 2019, 14(8):e0221043.
[6]
Song R H, Zhang J Q, Zhu Z Q, et al. Fault and self-repair for high reliability in die-to-die interconnection of 2.5D/3D IC[J]. Microelectron. Rel., 2024, 158:115429.
[7]
H Jeon, M Annavaram. Efficient RAS support for die-stacked DRAM[C]//. IEEE Int. Test Conf., 2014:1-10.
[8]
D K Maity, C Giri. Built-in self-prevention (BISP) for runtime ageing effects of TSVs in 3D ICs[J]. Integration, VLSI J., 2024, 94:102088.
[9]
H J Choi, S M Choi, et al. An experimental study on the TSV reliability:Electromigration (EM) and time dependent dielectric breakdown (TDDB)[C]// IEEE Int. Interconnect Technol. Conf., 2012:1-3.
[10]
K Chi, T Hwang. Architecture of ring-based redundant TSV for clustered faults[J]. IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 2016, 24(12):3437-3449.
[11]
Xu Q. Fortune:A new fault-tolerance TSV configuration in router-based redundancy structure[J]. IEEE Trans. Comput. Aided Design Integr. Circuits Syst., 2022, 41(10):3182-3187.
[12]
M B Sullivan, N Saxena, M O’Connor, et al.Characterizing and mitigating soft errors in GPU DRAM[C]// MICRO-54, 2021:641-653.
[13]
G Bak. Logic soft error study with 800-MHz DDR3 SDRAMs in 3x nm using proton and neutron beams[C]// IEEE Int. Rel. Phys. Symp., 2015:SE.3.1-SE.3.5.
[14]
D K Maity, C Giri. A cost-effective repair scheme for clustered TSV defects in 3D ICs[J]. Microelectron. Rel., 2022, 129:114460.
[15]
K N Dang, A B Ahmed, A B Abdallah, et al. TSV-OCT:A scalable online multiple-TSV defects localization for real-time 3-D-IC systems[J]. IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 2020, 28(3):672-685.
[16]
Zhang P. Predicting DRAM-caused node unavailability in hyper-scale clouds[C]// 52nd Annu. IEEE/IFIP Int. Conf. Dependable Syst. Netw. (DSN)., 2022:275-286.

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