Chiplet硬件安全综述:从攻击面分析到测试验证

朱沛霖; 李翔宇

doi:10.20193/j.ices2097-4191.2026.0088

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集成电路与嵌入式系统 ›› 2026, Vol. 26 ›› Issue (11) : 1-13. DOI: 10.20193/j.ices2097-4191.2026.0088

HIPI ICTS 2026 集成电路测试技术专刊

Chiplet硬件安全综述:从攻击面分析到测试验证

朱沛霖 ,
李翔宇 ^*

作者信息 +

A review of Chiplet hardware security: from attack-surface analysis to testing and verification

Zhu Peilin ,
Li Xiangyu ^*

Author information +

文章历史 +

摘要

Chiplet系统由多个独立设计、制造和测试的芯粒集合而成,为后摩尔时代高性能计算提供了重要路径。然而,新型Chiplet场景重构了传统单片系统级芯片(system-on-chip,SoC)的硬件安全边界,并对安全测试提出了新的要求。文中综述Chiplet硬件安全威胁、防御机制与测试验证研究,分析现有SoC安全测试技术在Chiplet场景下的适用性,归纳面向Chiplet场景的新型测试需求,并提出面向组合信任的芯粒生命周期安全测试与验证流程,同时分析测试基础设施可能引入的安全问题,最后总结相关技术的发展方向与关键挑战。

Abstract

Chiplet systems integrate multiple chiplets that are independently designed, manufactured, and tested, providing an important pathway for high-performance computing in the post-Moore era. However, emerging Chiplet-based architectures reshape the hardware security boundaries of conventional monolithic systems-on-chip (SoC) and introduce new requirements for security testing. This paper reviews research on hardware security threats, defense mechanisms, testing, and verification for Chiplet systems. It analyzes the applicability of existing SoC security testing techniques to Chiplet scenarios, summarizes emerging testing requirements, and proposes a Chiplet lifecycle security testing and verification process for compositional trust. The potential security risks introduced by test infrastructures are also examined, followed by a discussion of major research directions and key challenges.

导出引用

朱沛霖, 李翔宇. Chiplet硬件安全综述:从攻击面分析到测试验证[J]. 集成电路与嵌入式系统. 2026, 26(11): 1-13 https://doi.org/10.20193/j.ices2097-4191.2026.0088

Zhu Peilin, Li Xiangyu. A review of Chiplet hardware security: from attack-surface analysis to testing and verification[J]. Integrated Circuits and Embedded Systems. 2026, 26(11): 1-13 https://doi.org/10.20193/j.ices2097-4191.2026.0088

中图分类号： TP872 (远距离控制和信号、远距离控制和信号系统)

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