面向SoC内存的流水线奇偶校验电路设计与优化
马敬博, 张光达, 王会权, 裴秉玺, 方健, 黄成龙, 罗慧, 蒋艳德
Design and optimization of pipelined parity check circuit for SoC memory
MA Jingbo, ZHANG Guangda, WANG Huiquan, PEI Bingxi, FANG Jian, HUANG Chenglong, LUO Hui, JIANG Yande
集成电路与嵌入式系统
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2026, (4): 26
-33
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DOI: 10.20193/j.ices2097-4191.2025.0137
