Physical Unclonable Functions (PUFs) can be regarded as a "chip fingerprint" with lightweight, unpredictable, and difficult to clone characteristics, and have become an important component of IoT hardware security mechanisms. However, the implementation of traditional PUFs requires the addition of FPGA or dedicated integrated circuits at the hardware level, which will increase hardware costs. For billions of existing IoT embedded devices, it is difficult to increase PUF security attributes through hardware modifications. Therefore, we discuss the promising method to implement these intrinsic PUFs on commercial off-the-shelf devices and explore the potential applications of intrinsic PUFs. We will provide a systematic review of existing IPUFs, particularly Memroy based Intrinsic PUFs (MIPUFs), and discuss the feasibility and future development directions of IPUFs in existing systems, in order to promote the engineering application of this technology.

Trusted execution technology for processors is a viable solution for protecting sensitive information,providing a secure and isolated environment for sensitive information processing to ensure information security and privacy protection.However,trusted execution technology for processors faces threats from various attacks.To systematically understand the research on vulnerability exploration in processor trusted execution technology,this paper first introduces trusted execution technologies such as SEV in AMD,SGX in Intel and TrustZone in ARM.Then,the methods of vulnerability research under different processor platforms are introduced.Finally,this paper discusses the potential applications of trusted execution technology in the field of industrial control system,and forecasts its role in ensuring the security of industrial control systems and points out directions for future research.

Electromagnetic fault injection (EMFI) has become an effective fault injection attack technique threatening integrated circuit (IC) security.Existing research has demonstrated that EMFI perturbs circuits' internal states by inducing parasitic current on the IC power grid.Finite element analysis of the power grid under EMFI shows that the induced current could increase the IR drop of the power grid,leading to circuit faults.Therefore,to address this problem,we propose a power supply port placement optimization approach which reduces the effect of the induced current.The experiment results show that by optimizing the positions of the power supply ports,the worst IR drop can be reduced by 40%,enhancing the robustness of the power grid.

Aiming at the potential security issues arising from the existing deep learning edge applications relying on non-domestic FPGA architectures and encrypted IP implementations,which are difficult to quickly deploy on domestic FPGA platforms with insufficient IP and still under development,a neural network hardware deployment framework towards domestic FPGA is designed to achieve secure,autonomous and controllable deployment of domestic FPGA neural networks.In addition,the fast pipelined convolutional circuit and the im2col conversion circuit are designed to rapidly compute the systolic array.The experimental results demonstrate that the framework is capable of generating networks,such as Lenet5,with up to 147.8 GOPS for 16-bit data type and 0.024 ms running time,which represents a 5.13x improvement in throughput and a 6.67x decrease in time,respectively.An evaluation of im2col operation on RTL design yields up to 124.9x gains over CPU on Intel Xeon E-2276M.

Post-quantum cryptography has become a research hotspot in the current security field. In this paper, a secure SoC design scheme based on post-NIST quantum cryptography is proposed by studying Saber algorithm, which is a candidate of post-NIST quantum cryptography competition. The scheme firstly analyzes the hardware architecture of the algorithm, optimizes operations such as matrix operation and numerical splicing to improve hardware efficiency, and uses secondary verification to enhance the security of the decryption process of the algorithm, design Hash random number expansion generation module, encryption and decryption module and data storage and random number seed generator to complete the Saber algorithm hardware IP Core. On the basis of RISC-V processor, bus and interface circuit, a secure SoC based on post-quantum cryptography is designed with clock gating technology. The experimental results demonstrate that the area of the designed security SoC chip is 2.6 mm², with an equivalent logic gate count of 90k. The chip core area accounts for 75.2%, the PAD area accounts for 24.8%, and the chip power consumption is 9.467 mW.