Neural ordinary differential equation (ODE) network inference in Von Neumann architectures faces problems like the "power wall" and "memory wall". Traditional in-memory computing architectures also suffer from excessive time and power consumption due to numerous digital-to-analog and analog-to-digital conversions. To address these issues, we propose a fully analog compute-in-memory architecture for Neural ODEs based on RRAM to achieve fully analog data flow in network inference. The simulation is completed on the Cadence Virtuoso platform, which includes RRAM device, array, and the peripheral circuits. The test is performed on a 40 nm RRAM test platform and differential input/output PCB, achieving functional verification of the entire system. Experiments and evaluations of the classification tasks of Neural ODEs are conducted with testing errors, ultimately proving the functionality and reliability of the architecture. This lays a solid foundation for subsequent hardware implementation and application deployment.

The growing demand for massive data processing such as artificial intelligence has greatly promoted the development of chiplet integration technology, which further imposes technical requirements on FC-BGA substrates, including large size, low warpage, electrical performance and high reliability. The late-model glass core substrate has attracted extensive attention owing to its intrinsic low dielectric coefficient, high thermal stability and chemical inertness. However, current glass core substrate technology remains in the initial stage of mass production, lacking comprehensive, reliable and standardized methods of producation, application and testing. This article overviews the history, characteristics, and present challenges of glass core substrate. It also provides a summary and prospect on the future applications of glass core substrate in chiplet integration.

Neural network models demand high processor performance and energy efficiency. The memory-computing integrated architecture is an energy-efficient solution. This paper introduces a digital interface simulation scheme to address simulation verification challenges in analog memory-computing integrated designs and improve simulation efficiency in large-scale computing scenarios. The scheme analyzes SRAM-based memory-computing integration and combines the SPICE model with a digital control circuit. This enables the use of digital methods for simulation and verification, potentially boosting development efficiency. An evaluation system comparing the digital interface simulation with traditional analog circuit simulation reveals that the new solution increases simulation speed by more than 2 times and configuration efficiency by more than 1 000 times. This research is supported by the key research and development program of the ministry of science and technology (2021YFB3601300), and this research has been validated with tape-out at the 180 nm process node, demonstrating the efficiency advantages of the digital interface simulation scheme for memory-computing integrated design in large-scale computing.

In industrial control algorithms, the calculation of mathematical functions typically requires a large number of clock cycles, affecting the performance of the algorithms. This paper conducts an in-depth analysis and comparison of related methods for calculating floating mathematical functions, and designs a piecewise table lookup polynomial fitting method based on the Remez algorithm. This method is suitable for hardware circuit implementation to calculate mathematical functions. At the same time, the corresponding hardware circuits are implemented in the form of RISC-V custom instructions, closely coupled with the RISC-V processor core. The experimental results show that compared with no custom extension instructions, the processor's delay in calculating mathematical functions is reduced by 93.62%. Compared with the method of calculating mathematical functions using the CORDIC instruction set, the calculation delay is reduced by 79.83%. This achievement provides new ideas and solutions for RISC-V architecture embedded microprocessors with low-cost, high real-time requirements.

To achieve high parallel computing, fully homomorphic encryption hardware acceleration systems require the instantiation of a large number of cryptographic primitive operation units. As the most crucial primitive operation in fully homomorphic encryption, the circuit implementation area of modular multiplication significant impacts the overall area of the acceleration system. Addressing issues such as excessive resource usage, limited parameter, and dependency on macro core IPs in existing modular multiplier designs, this paper presents an efficient Montgomery modular multiplier based on FPGA. At the algorithmic level, the multiplier reduces the computational load through techniques such as NTT-Friendly modulus characteristics, compression, and encoding. At the circuit level, it minimizes resource through methods like time-division and data integration. Furthermore, the multiplier supports parameter configuration to implement Montgomery modular multiplication for different widths. Experimental results demonstrate that, for a 32-bit width, the designed Montgomery modular multiplier operates at a clock frequency of 223 MHz with a latency of 26.9 ns, utilizing 1 313 LUTs and 213 FFs. Compared to the baseline, the resource consumption is reduced by 32% on average, while the latency is improved by 16% on average, making the design more flexible and highly applicable.

A power integrity analysis is conducted for the layout and routing design of a domestic power verification board targeting a 48 V power input, with an output voltage of 0.8 V and a current requirement of 1 000 A. A simulation design strategy based on the power distribution network (PDN) is proposed. In the initial stage, an optimal layout is selected by comparing the voltage drop simulation results with different PCB layouts. Then, through simulation analysis of the power plane and via current carrying capacity, the vias are optimized. The optimization measures significantly reduced the voltage drop by 14.5 mV, decreased the plane circuit density by 61%, lowered power system loss by 17.2 W, and halved the via current. Moreover, the thermal effect of using a heat sink is simulated, and the results show that the highest temperature dropped by 27.81 ℃ after the application of the heat sink. Finally, using power plane resonance simulation analysis, the power plane resonance noise is successfully controlled within 0.001% of the output voltage. After board fabrication and actual measurement, the ripple noise of the verification board was controlled within 1% of the rated output voltage, and the overall efficiency exceeded 90%, reaching an industry-leading level. The results indicate that the simulation process strategy proposed in this paper can effectively improve the efficiency of PCB design, and avoid power integrity risks, such as excessive voltage drop loss, overcurrent, and overheating.

The inherent capacitor mismatch resulting from process variations is a significant impediment in the designing of high-resolution Analog-to-Digital Converters. Various calibration methods have been previously introduced, often employing additional circuits or external controllers, albeit at the expense of increased silicon area or intricate operational complexities. In this work, we have established the relationship between capacitor mismatches, output deviation, and Total Harmonic Distortion (THD) in capacitor Digital-to-Analog Converters. Consequently, the statistical distribution of expected THD under certain mismatch can be derived. After that, we propose a new compensation strategy that adopts the Dynamic Element Matching (DEM) technique to conventional cyclic ADCs with minimum hardware cost and implement this compensation scheme in a cyclic-pipelined ADC. We reassess the performance of the proposed ADC based on the formulated theory. Importantly, the measurement results of the cyclic ADC have not only confirmed the validity of our proposed theory but also demonstrated the robust performance of the simplified version of the DEM algorithm. This work is constructive for performance estimation in other high-precision ADC designs.

This study developed a Field-Controlled Enhancement Backside-Illuminated Single-Photon Avalanche Diode (SPAD) device using a simulation design platform. By adjusting the electric field in the avalanche region of the backside-illuminated SPAD, the photon detection efficiency was further improved, and the dark count rate was reduced. Simulation results indicate that the SPAD design effectively enhances electron multiplication efficiency through the synergistic effect of horizontal and vertical electric fields, achieving a peak detection efficiency of 50.1%. At an excess bias voltage of 3 V, the dark count rate decreased to 764 Hz. The study compares and analyzes the effects of different depletion layer thicknesses and P-Well radius on the performance of the field-controlled enhanced backside SPAD device, determining the optimal structural dimensions. The results provide a new technical approach for high-precision photoelectric detection applications based on SPAD and lay the groundwork for further development and application of SPAD technology in scientific research and industrial applications.

To address the demands of digital acquisition of vital signs signals and continuous blood pressure prediction,this paper designs and constructs a continuous blood pressure prediction system based on two-dimensional (2D) convolution.The system hardware adopts ESP32 module,AD8232 module and PulseSensor sensor to collect the human electrocardiography (ECG) and photoplethysmography (PPG) signal data,which are then transmitted to the server through the MQTT protocol for the consequent processing.Regarding the algorithms of this paper,a neural network model using ECG and PPG signals was designed and trained to predict continuous human blood pressure,employing the Gramian angular difference field (GADF),2D convolution,and model pruning techniques.The performance of the continuous blood pressure prediction model is verified on both classic open-source datasets and self-collected datasets.This system proposed in this paper provides a practical reference scheme for the vital signs signal acquisition and continuous blood pressure prediction.

Voting-based classifiers are widely used in many A.pngicial Intelligence (AI) applications.In their implementation,memories that store all known data are prone to suffer different effects like radiation and physical variations,causing soft errors and can even change the classification results.Therefore,error-tolerance must be achieved in these memories for safety-critical applications.Existing error-tolerant techniques commonly utilize error correction codes,however,the memory redundancy they introduce further increases the burden of storage.In this paper,a redundancy-free technique is proposed by focusing on the impact of errors on the classification performance,instead of the error itself.It can recover the error-free classification results under errors by exploiting the flipped data.A k nearest neighbor classifier is taken as a case study to evaluate the proposed technique.The simulation results show that the proposed scheme offers almost full error tolerance without incurring any memory redundancy,moreover,it significantly reduces the hardware overheads for protection circuits compared to existing techniques.

In high-speed wireline communication,clock-forwarding receivers requires the de-skew circuit to achieve the optimal sampling relationship between the clock and the data,and to ensure the synchronization of multiple data channels.A global de-skew scheme is proposed in the paper,which only uses one data and clock channel for alignment,and implements multi-channel data synchronization by clock delay matching and distribution techniques,reducing the power and area overhead by the independent de-skew circuit for each channel.The proposed receiver consists of 8 data channels,1 half-rate forwarded clock channel,and a global de-skew circuit based on the delay-locked loop.Based on 180 nm CMOS technology,at a data rate of 2.5 Gb/s,it can remove any skew between the input clock and data,and obtain the sampling phase at the center of the data eye,with the ability of clock duty cycle calibration.At a supply voltage of 1.8 V,the total power consumption of the proposed receiver is 187 mW,occupying the area of 0.16 mm²,saving 45.2% and 62.8% of power and area overhead,respectively,compared with the independent de-skew scheme for each channel.

High-speed extra short reach (XSR) wireline interfaces are an important technical solution for chiplets interconnection.The traditional continuous time linear equalizer (CTLE) based on current mode logic (CML) has gradually failed to meet the demand for high-density,miniaturization,and low-power consumption of chiplet data interfaces due to the use of high supply voltage and passive components.To address this problem,this paper proposes an inverter-based CTLE with mid-frequency compensation (MFC) to transmit 28 Gb/s non-return to zero (NRZ) signals as well as 56 Gb/s 4-level pulse amplitude modulation (PAM4) signals in XSR applications.The design is implemented in a 28 nm CMOS process with a core area of only 400 μm².After an XSR channel at -9.4 dB@14 GHz,the post-layout simulation results show that the proposed CTLE improves the eye width of the 28 Gbaud NRZ and PAM4 signals by 0.14 UI and 0.41 UI,and the eye heights by 328 mV and 119 mV,respectively.The power consumption is 6.12 mW at 56 Gb/s PAM4 signaling.