The real-time simulation of new power system puts forward higher requirements for CPU-FPGA heterogeneous computing and multi-FPGA distributed computing, in which communication efficiency may become one of the bottlenecks. Given the current limitations of Gigabit Ethernet in bandwidth and real-time performance, this paper proposes an FPGA-based lightweight design of 10 GbE high-bandwidth low-latency interface. PHY is built based on the GT to achieve low latency and high reliability. In the UDP stack, alternating caching and queuing with priority are adopted to improve data throughput and balance instantaneous load. The on-board test results show that the design achieves low hardware resource consumption, a maximum transmission bandwidth of 9.70 Gb/s, an average transmission delay of 0.45 μs and stable interactions between protocol layers without interference, which provides efficient communication support for the simulation of power system and other applications.

Aiming at the problems such as excessive resource overhead, high memory consumption, and low routing efficiency in the routing process of large-scale FPGAs, a resource-friendly coarse-grained parallel routing method tailored for large-scale FPGAs is proposed. First, a non-intrusive data optimization technique is proposed to reduce the resource overhead and memory consumption caused by the routing resource graph, addressing the memory explosion problem resulting from the increasing scale of FPGAs and providing a data foundation for the routing method. Second, adaptive load balancing and high-fanout net partitioning techniques are introduced to tackle the low parallelism in coarse-grained parallel routing, thereby improving the overall routing efficiency. The experimental results show that the proposed coarse-grained parallel routing method for large-scale FPGAs can achieve a 3.18× speedup in runtime while reducing resource and memory consumption by 90%, without compromising performance metrics such as wirelength and critical path delay.

Neural networks are representative algorithms of artificial intelligence, but their huge number of parameters poses new challenges to their hardware deployment at the edge. On the one hand, for the flexibility of applications, computing hardware is required to be able to transfer the deployed model between tasks through parameter fine-tuning at the edge. On the other hand, in order to improve computing energy efficiency and performance, it is necessary to implement large-capacity on-chip storage to reduce off-chip memory access costs. The recently proposed ROM-SRAM hybrid compute-in-memory architecture is a promising solution under mature CMOS technology. Thanks to the high-density ROM-based compute-in-memory, most of the weights of the neural network can be stored on the chip, cutting the reliance on off-chip memory access. Meanwhile, SRAM-based compute-in-memory can provide flexibility for edge compute-in-memory based on high-density ROM. To expand the design and application space of ROM-SRAM hybrid compute-in-memory architecture, it is necessary to further improve the density of ROM-based compute-in-memory to support larger networks and explore solutions to obtain greater flexibility through a small amount of SRAM compute-in-memory. This paper introduces several common techniques to improve the memory density of ROM-based compute-in-memory, as well as the neural network fine-tuning methods based on the ROM-SRAM hybrid compute-in-memory architecture to improve flexibility. The solutions to the deployment of ultra-large-scale neural networks and the bottleneck of dynamic matrix multiplication in large language models with long sequences are discussed, and the outlook for the broad design space and application prospects of ROM-SRAM hybrid compute-in-memory architecture is provided.

With the rapid advancement of cutting-edge technologies such as artificial intelligence and quantum computing, the demand for high-performance computing chips continues to increase. However, traditional von Neumann architectures are increasingly constrained by the memory wall and power wall, making it difficult to meet the computing demands of data-intensive applications. Cryogenic in-memory computing combines the superior electrical properties of cryogenic CMOS devices with the high bandwidth and low latency advantages of in-memory computing architectures, providing a new solution to overcome computing bottlenecks. This review summarizes the key characteristics of CMOS devices and various memory media at cryogenic temperatures, systematically reviews representative architectures, key implementations, and performance metrics of cryogenic in-memory computing in the fields of artificial intelligence and quantum computing. Moreover, this review analyzes the challenges and development trends at the levels of device technology, circuit systems, and EDA tools.

To address the limitations of SoC platforms in supporting professional video transmission in airborne environments, this paper proposes an FPGA-assisted airborne video processing and transmission system based on the RK3588. Serving as the core processing unit, the RK3588 is responsible for real-time video stream acquisition, target detection, and image enhancement. The processed video is then transmitted to the FPGA module via the MIPI-DSI2 interface. Considering that the MIPI-DSI2 interface is not suitable for long-distance or high-interference transmission scenarios, the FPGA module adopts a triple-frame buffering mechanism and performs image format conversion and SDI encoding to generate video streams compliant with the SMPTE standard. This ensures reliable video transmission quality and system stability under complex airborne conditions. The experimental results demonstrate that the proposed system effectively meets the demands of high-performance video processing and transmission in airborne applications.

This study proposes a design method for a multi-channel DMA controller based on the AMBA AHB bus protocol. It puts forward a relatively complete design scheme for the multi-channel DMA controller, and provides detailed module designs. Through the multi-channel design, channel arbitration enables the two channels with the highest priority to alternately read and write, thereby preventing prolonged bus occupation by a single channel that could block other transfers. And resource consumption is reduced through time division multiplexing. Moreover, potential interactions with external devices are considered, improving transmission efficiency while reducing overall resource utilization.

The PCIe interface bus enables low-latency, high-bandwidth data transmission between CPU and FPGA, with the key factor being the design of a DMA engine, allowing data transfer without CPU intervention. However, the majority of current CPU+FPGA data transmission solutions are based on foreign FPGA devices from Xilinx. There is a severe shortage of commercial IP cores for domestic FPGA, making it challenging to port these solutions to domestic FPGA platforms. To address this limitation, this paper designs a PCIe-based DMA engine and its corresponding driver on a domestic FPGA platform. The design encapsulates the parsing of transaction layer packets within the PCIe protocol stack, thereby reducing the development complexity of PCIe-based applications on domestic FPGA devices. The experimental results demonstrate that the DMA engine achieves a read throughput of 784 MB/s and a write throughput of 800 MB/s via PCIe 2.0 x2 bus, reaching 82% and 84% of the theoretical maximum bandwidth of PCIe 2.0 x2.

With the gradual adoption of embedded systems in industrial control systems, the need to establish a data-centric digital factory to support production management, scheduling decisions, and the intelligent production resources configuration has become increasingly prominent. Among these, efficient and reliable data transmission methods play a crucial role in digital construction and serve as a prerequisite for the orderly operation of the entire embedded system. Data Distribution Service (DDS), as a high-performance communication middleware, provides a specification for data sharing between different systems and has received widespread attention in recent years. However, current data distribution services for embedded platforms exhibit two gaps: embedded devices cannot directly participate as communication nodes, and time-critical messages lack real-time guarantees when network resources are contended. To address this issue, this paper proposes an optimized strategy based on software and hardware co-design, focusing on the operational characteristics of DDS. It involves a dedicated SRAM for rapid loading of DDS modules and utilizes DMA technology to improve data interaction energy efficiency, including multi-level parallel computing technology based on module decoupling and a high-availability software design strategy based on the Master-Works pattern. Testing and verification were conducted on STM32H4, and the analysis results show that the method designed in this paper is suitable for real-time performance analysis of data distribution services in network environments. Compared to centralized data centers, the packet loss rate is reduced by 5%, and the data transmission efficiency is improved by approximately 8%.

With the development of high-power microwave technology, strong electromagnetic technologies such as ultra-wideband and high power pose an increasing threat to electronic equipment. Using high-power microwaves to destroy electronic information equipment has become an important way to interfere with communication systems. The protection of high-power microwaves is mainly divided into front-door protection and back-door protection. As an important microwave device for front-door protection, the limiter is also facing higher and higher requirements. This paper first introduces the device characteristics and performance advantages of GaN materials and Schottky diodes, and then introduces the principle and circuit structure of the limiter based on semiconductor devices, and discusses the research progress of the new generation of high-power microwave limiting technology based on GaN Schottky diodes.

The space radiation-resistant optical transceiver module is capable of realizing high-speed parallel optical-electrical conversion and transmission functions within the space application environment. By employing optical means, it achieves the transmission of high-speed signals, thereby addressing the bottleneck issue of data transmission in spaceborne systems and reducing the overall system weight through an optimized transmission architecture. This advancement holds significant milestone value. This paper provides a detailed analysis of the module's working principles, structural composition, and associated characteristics. Furthermore, it evaluates the functional performance, quality reliability, and environmental adaptability of a particular 12-channel parallel optical transceiver module that is resistant to radiation, considering its specific application context. Based on the product definition and user requirements, a standardized index system and assessment criteria have been developed in a forward-thinking approach, offering guidance for the standardization of novel optical module products.

The electronic controller of an aero-engine is a complex circuit system designed with numerous large-scale integrated circuits as the core. The traditional contact-based fault injection and detection methods relying on physical probes fail to meet the testability design requirements of such complex circuits. This paper proposes a fault injection and detection method based on boundary scan for the core circuit of the aero-engine electronic controller. Through the analysis of the core circuit, a boundary scan daisy chain and a boundary scan controller are designed, possessing the ability to conduct fault injection and detection based on the interconnection between chips and the boundary scan units inside the chips. The fault injection and detection functions of the two methods are verified, combined with the overspeed protection logic of the engine.

This paper reviews the design and optimization of bioimpedance detection chips, focusing on the applicable scenarios of dual-electrode and quad-electrode and their trade-offs in measurement accuracy and portability. According to different detection requirements, the implementation principles and characteristics of ADC method, DAC method, successive approximation method, half-sine DAC method and baseline elimination technology are discussed in detail. Studies have shown that dual-electrode combined with efficient DAC method has significant advantages in portable devices, while the four-electrode configuration is suitable for high-precision impedance measurement scenarios. This paper provides theoretical support for the design of bioimpedance detection chips and looks forward to its application prospects in wearable medical devices and dynamic monitoring.

A power integrity analysis is conducted for the layout and routing design of a domestic power verification board targeting a 48 V power input, with an output voltage of 0.8 V and a current requirement of 1 000 A. A simulation design strategy based on the power distribution network (PDN) is proposed. In the initial stage, an optimal layout is selected by comparing the voltage drop simulation results with different PCB layouts. Then, through simulation analysis of the power plane and via current carrying capacity, the vias are optimized. The optimization measures significantly reduced the voltage drop by 14.5 mV, decreased the plane circuit density by 61%, lowered power system loss by 17.2 W, and halved the via current. Moreover, the thermal effect of using a heat sink is simulated, and the results show that the highest temperature dropped by 27.81 ℃ after the application of the heat sink. Finally, using power plane resonance simulation analysis, the power plane resonance noise is successfully controlled within 0.001% of the output voltage. After board fabrication and actual measurement, the ripple noise of the verification board was controlled within 1% of the rated output voltage, and the overall efficiency exceeded 90%, reaching an industry-leading level. The results indicate that the simulation process strategy proposed in this paper can effectively improve the efficiency of PCB design, and avoid power integrity risks, such as excessive voltage drop loss, overcurrent, and overheating.

The article is based on the LMK04828 high-performance clock chip, combined with the multi-board cascade clock multi-channel JESD204B synchronous sampling application scenario. It analyzes the impact of the division factor on the phase certainty of the clock output from two directions: the divider and the phase-locked loop. On this basis, a cross-board cascade clock synchronization verification system is designed, and the system is explained in terms of mode configuration precautions, the second-level phase-locked loop divider coefficient conditions, and timing constraints between the SYNC signal and SYSREF. A specific synchronization control process is provided. Finally, through repeated power-up and resynchronization experiments, as well as experiments of repeatedly triggering the SYSREF pulse output after a single power-up, it is confirmed that the phase relationship of the clock output from the cross-board cascade clock chip remains unchanged, verifying the effectiveness of the synchronization scheme and phase certainty.

With the rapid increase of data volume in today's era, higher requirements are put forward for data transmission technology, especially in terms of transmission speed, stability and reliability. Traditional single channel LVDS data transmission system generally achieve transmission rates of only a few hundred Mb/s when transmitting over long distances, which is insufficient for high-speed data transmission needs. To address this challenge, this paper proposes a comprehensive optimization scheme. In terms of hardware, two groups of four channel LVDS chips are used as the high-speed data interface, enabling eight channel LVDS transmission and thereby improving the data transmission rate. However, as the rate increases, the probability of error code generation due to crosstalk and electromagnetic interference also increases. Therefore, it is necessary to cooperate with the anti-interference ability and long-distance transmission ability of dedicated LVDS data driver and cable equalizer system. In addition, RS encoding and decoding technology is introduced into the software logic to achieve error correction within a certain range. With automatic retransmission technology and CRC verification, the reliability of data transmission is improved. After extensive tests, the proposed design can finally achieve 4 000 Mb/s zero error transmission under 80 m twisted pair shielded cable.

High-speed SerDes rates have progressed from 56 Gb/s to 112 Gb/s and beyond. Maintaining signal integrity at such ultra-high speeds while balancing power consumption, reliability, flexibility, and cost-effectiveness is a hot topic in current research. This paper reviews key technologies for 112 Gb/s SerDes from four perspectives: transmitter, receiver, clock structure, and low-power techniques, based on the current mainstream architecture of analog-to-digital conversion and digital signal processing. This exploration is provided as a reference for research related to high-speed SerDes technology.