The real-time simulation of new power system puts forward higher requirements for CPU-FPGA heterogeneous computing and multi-FPGA distributed computing, in which communication efficiency may become one of the bottlenecks. Given the current limitations of Gigabit Ethernet in bandwidth and real-time performance, this paper proposes an FPGA-based lightweight design of 10 GbE high-bandwidth low-latency interface. PHY is built based on the GT to achieve low latency and high reliability. In the UDP stack, alternating caching and queuing with priority are adopted to improve data throughput and balance instantaneous load. The on-board test results show that the design achieves low hardware resource consumption, a maximum transmission bandwidth of 9.70 Gb/s, an average transmission delay of 0.45 μs and stable interactions between protocol layers without interference, which provides efficient communication support for the simulation of power system and other applications.