With the rapid advancement of cutting-edge technologies such as artificial intelligence and quantum computing, the demand for high-performance computing chips continues to increase. However, traditional von Neumann architectures are increasingly constrained by the memory wall and power wall, making it difficult to meet the computing demands of data-intensive applications. Cryogenic in-memory computing combines the superior electrical properties of cryogenic CMOS devices with the high bandwidth and low latency advantages of in-memory computing architectures, providing a new solution to overcome computing bottlenecks. This review summarizes the key characteristics of CMOS devices and various memory media at cryogenic temperatures, systematically reviews representative architectures, key implementations, and performance metrics of cryogenic in-memory computing in the fields of artificial intelligence and quantum computing. Moreover, this review analyzes the challenges and development trends at the levels of device technology, circuit systems, and EDA tools.

As Moore’s Law slows down, domain-specific SoC (DSSoC) has emerged as a promising energy-efficient design strategy by integrating domain-specific accelerator (DSA). However, the design process for DSSoC remains highly complex, leading to prolonged development cycles and significant labor effort. Recent advances in large language models (LLMs) have introduced new methodologies for agile chip design, demonstrating substantial potential in code and EDA script generation. In this work, an LLM-based multi-agent framework for DSSoC design is proposed, which consists of end-to-end design stages from architecture definition to code generation and EDA physical implementation. The approach is validated through two case studies involving 2-to 4-week SoC designs at process nodes of 22 nm and 7 nm. The evalautions show the generated SoCs achieve energy efficiency improvements of 4.84× and 3.82×, compared to SoCs generated by the existing framework.

The real-time simulation of new power system puts forward higher requirements for CPU-FPGA heterogeneous computing and multi-FPGA distributed computing, in which communication efficiency may become one of the bottlenecks. Given the current limitations of Gigabit Ethernet in bandwidth and real-time performance, this paper proposes an FPGA-based lightweight design of 10 GbE high-bandwidth low-latency interface. PHY is built based on the GT to achieve low latency and high reliability. In the UDP stack, alternating caching and queuing with priority are adopted to improve data throughput and balance instantaneous load. The on-board test results show that the design achieves low hardware resource consumption, a maximum transmission bandwidth of 9.70 Gb/s, an average transmission delay of 0.45 μs and stable interactions between protocol layers without interference, which provides efficient communication support for the simulation of power system and other applications.

A communication interface for NoC and Flash controller is designed, mainly consisting of request path module, protocol conversion module and response path module. The request path module can complete data verification and cross-clock processing of the request packet sent by NoC. The protocol conversion module converts the processed packet into configuration instructions in the form of AHB bus signal, configuring the Flash controller and controlling the Flash storage device to complete erasing, reading and writing operations. When Flash storage devices generate response data, the protocol conversion module packs the received response data into response packets and feeds it back to NoC through the response path module. This communication interface can improve the packet transmission efficiency between NoC and Flash controller to solve the difficulties of efficient packet transmission interaction of multi-chiplet interconnected data, providing the technical foundation for the development of multi-chiplet integration technology.

Bioimpedance measurement technology serves as a vital tool for medical diagnosis and health monitoring in various emerging medical instruments, in which the high-precision readout circuit is a crucial module for achieving accurate diagnoses. Traditional readout circuits in bioimpedance measurement systems often utilize SAR ADCs, which can hardly achieve an accuracy exceeding 12 bits to meet the increasingly high-precision demands for bioimpedance readout without calibration. To deal with this issue, this paper presents a 24-bit incremental Σ-Δ ADC designed for bioimpedance measurement which adopts a 3^rd-order, 4-bit, single-loop feedforward structure to reduce quantization noise while accelerate the conversion speed. The design incorporates data weighted averaging (DWA) technique to mitigate the nonlinearity caused by multibit feedback DAC’s mismatch, significantly enhancing the ADC’s accuracy. In addition, system-level chopping is employed to eliminate systematic offset in the ADC frontend. A configurable digital filter is designed to achieve flexible tradeoff between measurement time and by configuring different oversampling ratios (OSR). The ADC is fabricated using a 180 nm process, with measurement results under an OSR of 128 showing that the ADC achieves an ENOB of 17.80, a SNR of 108.89 dB, a THD of -113.29 dB, an equivalent input RMS noise of 2.95 μV_RMS. The power consumption is 930 μW for the whole ADC chip.

Hyperdimensional computing (HDC), an emerging computing paradigm drawing inspiration from the human brain, boasts several notable advantages, including low complexity, exceptional robustness, and high interpretability. Consequently, it holds immense potential for a wide array of applications in edge-side applications. HDC serves as an innovative approach that mimics the human brain's information processing mechanisms. By leveraging hyperdimensional vectors and straightforward logical operations, it can accomplish complex cognitive functions. Instead of relying on the complicated architecture of neural network with multi-layers, it employs a lightweight encoding-querying process, paving a fresh technical avenue for the development of highly efficient edge-side artificial intelligence chips. This review provides a meticulous and in-depth analysis of the theoretical foundations and the progressive development of algorithms within HDC, and thoroughly investigates the viability of implementing hardware acceleration techniques at every step of HDC. Based on this, this review focuses on the dedicated hardware for the querying step, summarizes the three implementation methods of FPGA, ASIC, and in-memory computing, and analyzes the advantages and disadvantages of different methods. Moreover, considering the prevalent shortcomings inherent in existing hardware for hyperdimensional querying, this review presents some most recent research advancements. Finally, the challenges confronting hardware for HDC are delineated, and the promising avenues for its future research endeavors are outlined.

Brain organoids are three-dimensional cell aggregates produced in vitro through the self-organization and differentiation of human pluripotent stem cells, which can partially recapiculate the structure and function of the brain in humans. Microelectrode array (MEA) technology is capable of high-throughput detecting the electrophysiological activities of brain organoids with low damage, and high spatiotemporal resolution, thereby providing an efficient platform for the functional characterization of brain organoid neural networks. The integration of brain organoids with MEA technology has attracted widespread attentions in the fields of nervous system development and disease mechanism research, biological neural network intelligent computing, and in vivo repair. In the area of nervous system development and disease mechanism research, MEA technology can long-term track the dynamic developmental process of brain organoids in real time and probe the pathogenesis of diseases by detecting the electrophysiological activities of brain organoids derived from various nervous system diseases. In the avenue of biological neural network intelligent computing research, brain organoids are excellent computing devices attributed to their heterogeneous three-dimensional network structures and plasticity. Therefore, a highly efficient computing platform with low energy cost can be constructed through interaction of brain organoids with MEA. Furthermore, MEA technology shows potential technical application prospects in nervous system repair based on brain organoids.

In recent years, with the widespread application of large models (such as GPT, LLaMA, DeepSeek, etc.), the computing power requirements and energy efficiency issues in the reasoning stage have become increasingly prominent. Although traditional GPU solutions can provide high throughput, they face challenges in power consumption, real-time performance and cost. FPGAs have become an important alternative for large model reasoning deployment with their customizable architecture, low latency determinism and high energy efficiency. This paper systematically reviews the network structure of large models and the reasoning implementation technology of large models on FPGAs, covering three major directions: hardware architecture adaptation, algorithm-hardware co-optimization and system-level challenges. At the hardware level, the focus is on the design of computing units and storage level optimization strategies; at the algorithm level, key technologies such as model compression, dynamic quantization and compiler optimization are analyzed. At the system level, challenges such as multi-FPGA expansion, thermal management and emerging storage-computing integrated architectures are discussed. In addition, this paper summarizes the limitations of the current FPGA reasoning ecosystem (such as insufficient tool chain maturity) and looks forward to future trends, including chiplet heterogeneous integration, photonic computing fusion and the establishment of a standardized evaluation system. The research results show that the architectural flexibility of FPGA gives it a unique advantage in the field of efficient reasoning of large models, but interdisciplinary collaboration is still needed to promote the implementation of the technology.

Computing-In-Memory (CIM) based on Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) is expected to be an effective way to overcome the "memory wall" bottleneck. This paper proposes a high-energy-efficient CIM design scheme for STT-MRAM in the time domain: a custom series-connected memory cell structure, through the series connection of transistors and complementary MTJ design, forms a magnetic resistance chain of multiple rows of memory cells in the computing mode, and combines a time-domain conversion circuit to convert the resistance value into a pulse delay signal. Further, a complementary series array architecture is designed, generating differential time signals through the separate storage of positive and negative weights to support signed number calculations. In terms of quantization circuit design, a Successive Approximation Register (SAR) Time-to-Digital Converter (TDC) is proposed, which adopts a structure combining a voltage-adjustable delay chain and a flip-flop. To achieve multi-bit multiply-accumulate operations, a signed number weight encoding scheme and a digital post-processing architecture are proposed. Through encoding weight mapping and digital shift-accumulate algorithms, the 8-bit input and 8-bit weight multiply-accumulate operation is decomposed into low 5-bit time-domain calculation and high-bit digital-domain calculation, outputting a 21-bit full-precision result. Based on the 28 nm CMOS process, the layout design and post-simulation were completed. At 0.9 V voltage, a 9-bit multiply-accumulate operation with a resolution margin of 270 ps was achieved, with an energy consumption of only 16 fJ per operation. The designed 5-bit SAR-TDC achieves high linearity conversion from time to digital. A 9 Kb time-domain CIM macrocell with an area of 0.026 mm² was designed, including a memory cell array, SAR-TDC module, computing circuit, and read-write control circuit. The macrocell can achieve energy efficiencies of 26.4 TOPS/W and 42.8 TOPS/W when performing convolutional layer and fully connected layer calculations, respectively, while achieving 8-bit precision calculation and an area efficiency of 0.523 TOPS/mm².

With the development of high-power microwave technology, strong electromagnetic technologies such as ultra-wideband and high power pose an increasing threat to electronic equipment. Using high-power microwaves to destroy electronic information equipment has become an important way to interfere with communication systems. The protection of high-power microwaves is mainly divided into front-door protection and back-door protection. As an important microwave device for front-door protection, the limiter is also facing higher and higher requirements. This paper first introduces the device characteristics and performance advantages of GaN materials and Schottky diodes, and then introduces the principle and circuit structure of the limiter based on semiconductor devices, and discusses the research progress of the new generation of high-power microwave limiting technology based on GaN Schottky diodes.

针对众核CPU芯片中缓存一致性片上网络（Network-on-Chip, NoC）缓存一致性监听及监听响应过程耗时过长的问题，提出多播和自适应路由2种技术来加速该过程。根据这2种技术的需求，设计了片上网络监听请求、监听响应数据包格式；并进一步设计实现了监听请求通道和监听响应通道的NoC路由器和8X8网络。设计实践表明，按照本文所提的NoC路由器在22nm工艺下大小为85940.3 或103518.5 ，8X8的监听请求及监听响应网络大小为5.57 ，复杂度可接受。通过仿真比较了单播和多播、确定性路由和自适应路由4种配置下监听及监听响应过程的耗时，仿真实验表明，在监听请求消息需要监听所有252个处理器核心时，本文所提技术可使1个监听请求消息的监听及监听响应过程耗时减少45%，且远小于DDR/HBM的访问延迟；倘若进一步在一致性节点(Point of Coherency, PoC)处采用Outstanding技术，本文所提技术可使32个监听请求消息的监听及监听响应过程耗时减少73%。仿真结果证实了所提多播和自适应路由技术的有效性。

With the rapid advancement of information technology and artificial intelligence, the increasingly complex functions of IoT terminal devices have resulted in significant security threats due to their limited hardware resources. To address this, this paper proposes a dual-mode configurable software PUF (Physical Unclonable Function) design based on the DSP IP core. This approach leverages the timing violation behavior characteristics of sampling registers and the combinational logic delay features within the DSP IP core of FPGA. First, the internal structure of DSP IP cores in Xilinx Artix-7 FPGA is analyzed, determining the clock cycle range for normal data transmission based on their combinational logic delay information and timing constraints. Next, two distinct operational modes are configured based on the required challenge bit length, with overclocked clocks applied to induce abnormal computational results through timing violation in the sampling registers. Finally, a hash algorithm and parity check are used to compress the abnormal data of varying bit lengths into a 1-bit PUF response. This design eliminates the need for additional bias extraction circuits and allows for flexible configuration of two different challenge bit lengths for the software PUF implementation without modifying the hardware structure. The experimental results demonstrate that both operational modes achieve a reliability of over 98%, with excellent uniqueness and resistance to machine learning attacks, thereby validating the proposed scheme's feasibility and advantages in terms of both security and practicality.

In this paper, an 8-bit current-steering Digital to Analog Converter(DAC) based on Metal Oxide Thin Film Transistor (MO-TFT) technology is designed, which includes a timing refresh module, a synchronous register circuit, a segmented decoding circuit, a switch driver circuit, a switch array and a current source array, a multiplexer network, and a random sequence generator. The timing refresh structure is designed in the digital circuit to solve the traditional bootstrap logic gate charge leakage caused by the current source switch driving voltage drop, to avoid the problem of sampling errors in low frequency signals. A differential dual decoding structure is proposed, so that the open and close signals could reach the switch driver circuit at the same time, ensuring the symmetry of the voltage rise and fall Windows in the driver circuit and reduced the output glitter. Meanwhile, the D flip-flop in the digital circuit and the logic gate in the decoder circuit are used to implement the driver enhancement circuit, guaranteeing the high bit unit current source in the analog circuit can be driven and the conversion rate is improved. Dynamic Elements Matching (DEM) technique is employed to improve the dynamic performance of DAC. The poster-simulation results show that the designed DAC has an area of 73 mm², a power consumption of 6.5 mW, an output current swing of 301.46 μA, a maximum conversion rate of 32 kS/s. Under the condition that the standard deviation of the random matching error of the unit current source is 0.1, the Spurious-Free Dynamic Range (SFDR) at the Nyquist frequency can reach 42.43 dB, the maximum Differential Nonlinearity (DNL) is 0.36 LSB, and the maximum Integral Nonlinearity (INL) is 1.75 LSB, meeting the requirements of flexible electronic systems for biomedical applications.

In order to solve the problems of MCU and DSP serial calculation widely used in permanent magnet synchronous motor control, insufficient dynamic accuracy and long development cycle of complex vector control algorithms, a vector control technology of Permanent Magnet Synchronous Motors (PMSM) based on domestic FPGA is proposed. By adopting the modular design methods of Hardware Description Language (HDL) and Electronic Design Automation (EDA), the dual closed-loop feedforward PI control strategy, Space Vector Pulse Width Modulation (SVPWM) algorithm, and the underlying key modules such as coordinate transformation and encoder feedback are independently designed, and the logic and timing simulation tests of key functional modules are carried out by Modelsim respectively. Finally, a PMSM vector control hardware system based on domestic FPGA is constructed. The SVPWM waveform test, the dynamic accuracy under multiple signal inputs such as step signal and square wave signal, and the chip performance test analysis are conducted, which verified the effectiveness of the design and implementation results of the proposed vector control technology for permanent magnet synchronous motor based on domestic FPGA.

This paper reviews the design and optimization of bioimpedance detection chips, focusing on the applicable scenarios of dual-electrode and quad-electrode and their trade-offs in measurement accuracy and portability. According to different detection requirements, the implementation principles and characteristics of ADC method, DAC method, successive approximation method, half-sine DAC method and baseline elimination technology are discussed in detail. Studies have shown that dual-electrode combined with efficient DAC method has significant advantages in portable devices, while the four-electrode configuration is suitable for high-precision impedance measurement scenarios. This paper provides theoretical support for the design of bioimpedance detection chips and looks forward to its application prospects in wearable medical devices and dynamic monitoring.

Electrical stimulation technology has been widely applied in various biomedical fields, including cardiac pacemakers, cochlear implants, muscle reconstruction, vision restoration, and epilepsy suppression. Compared to traditional drug therapies or surgical methods, electrical stimulation offers advantages such as reduced invasiveness, greater flexibility, improved recoverability, and the elimination of risks associated with drug dependency and addiction. Due to the advantages of integrated circuits, including low power consumption, high reliability, strong programmability, ease of multifunctional integration, and suitability for mass production, they have recently become the primary choice for designing electrical stimulators, meeting the demands for miniaturized, intelligent, and cost-effective biomedical applications. However, the integration of high-density electrodes with stimulation-generating circuits presents significant challenges in designing electrode-tissue interfaces. This paper begins with the electrode-tissue interface and provides a comprehensive overview of integrated circuit design for implantable electrical stimulators, including fundamental driver circuit topologies and high-performance complex designs. It emphasizes the analysis of the reliability and safety of biomedical implantable chips and introduces innovative designs that integrate stimulators with energy harvesting modules in closed-loop systems. This review also discusses the future directions of electrical stimulation technology and interface systems including our research group's work on electrical stimulation and interface circuits.

Neural networks are representative algorithms of artificial intelligence, but their huge number of parameters poses new challenges to their hardware deployment at the edge. On the one hand, for the flexibility of applications, computing hardware is required to be able to transfer the deployed model between tasks through parameter fine-tuning at the edge. On the other hand, in order to improve computing energy efficiency and performance, it is necessary to implement large-capacity on-chip storage to reduce off-chip memory access costs. The recently proposed ROM-SRAM hybrid compute-in-memory architecture is a promising solution under mature CMOS technology. Thanks to the high-density ROM-based compute-in-memory, most of the weights of the neural network can be stored on the chip, cutting the reliance on off-chip memory access. Meanwhile, SRAM-based compute-in-memory can provide flexibility for edge compute-in-memory based on high-density ROM. To expand the design and application space of ROM-SRAM hybrid compute-in-memory architecture, it is necessary to further improve the density of ROM-based compute-in-memory to support larger networks and explore solutions to obtain greater flexibility through a small amount of SRAM compute-in-memory. This paper introduces several common techniques to improve the memory density of ROM-based compute-in-memory, as well as the neural network fine-tuning methods based on the ROM-SRAM hybrid compute-in-memory architecture to improve flexibility. The solutions to the deployment of ultra-large-scale neural networks and the bottleneck of dynamic matrix multiplication in large language models with long sequences are discussed, and the outlook for the broad design space and application prospects of ROM-SRAM hybrid compute-in-memory architecture is provided.

PCIe and SRIO are the mainstream high-speed communication interface protocols. In the large data application scenario represented by artificial intelligence, achieving the compatibility of the above protocols is the key to build a large computing power system to break through the bottleneck of storage and computing power. In view of the above requirements, CIP interconnection core realizes multi-protocol conversion interaction such as PCIe, SRIO, DDR and NAND FLASH with a unified routing network. Among them, PCIe is the main human-computer interaction interface, and the construction of PCIe RP system is the basis of PCIe communication. The existing PCIe reading and writing devices based on operating system have some problems, such as high delay and poor operability. In order to solve the above problems, a PCIe RP system is built based on Cortex-M3 processor, and the corresponding drivers and software are developed, which realizes efficient and accurate data transmission between PCIe and various devices. On the basis of realizing the basic functions, the stability tests of 50 000 times, 100 000 times and 150 000 times of large-scale data interaction were completed respectively. The results show that the system has good stability in large-scale data interaction events. It provides a solution for data interaction between processor and PCIe.

Artificial intelligence devices are miniaturized devices that provide system functions, serving as hardware carriers and foundations for spatial environment perception, autonomous judgment, and autonomous task planning. Before being applied in aerospace, these new types of components still face many challenges such as maturity, reliability, radiation resistance, and aerospace applicability. Starting from the analysis of the current development status of artificial intelligence devices both domestically and internationally, this article examines the challenges and countermeasures faced by the aerospace applications of artificial intelligence devices, provides typical cases of quality assurance for artificial intelligence devices, and summarizes relevant suggestions for the subsequent aerospace applications of artificial intelligence devices.

The space radiation-resistant optical transceiver module is capable of realizing high-speed parallel optical-electrical conversion and transmission functions within the space application environment. By employing optical means, it achieves the transmission of high-speed signals, thereby addressing the bottleneck issue of data transmission in spaceborne systems and reducing the overall system weight through an optimized transmission architecture. This advancement holds significant milestone value. This paper provides a detailed analysis of the module's working principles, structural composition, and associated characteristics. Furthermore, it evaluates the functional performance, quality reliability, and environmental adaptability of a particular 12-channel parallel optical transceiver module that is resistant to radiation, considering its specific application context. Based on the product definition and user requirements, a standardized index system and assessment criteria have been developed in a forward-thinking approach, offering guidance for the standardization of novel optical module products.