To meet the requirements of overcurrent protection for industrial equipment, a modular design-based electronic circuit solution is proposed, aiming to achieve precise current detection and rapid protection response. The modular design architecture integrates current sensing amplifier, hysteresis comparator and relay to work collaboratively: the current sensing amplifier is used to achieve signal acquisition with 0.1mA level accuracy, the hysteresis comparator is used to set the protection threshold, and the solid-state relay is used to control the circuit's on-off. Experimental results show that when the current exceeds the set threshold, the circuit completes the disconnection action within 10ms, and remains in the open state even when the threshold current drops below the threshold, avoiding false recovery. After multiple cycle tests, the protection action accuracy rate reaches 98.4%, effectively eliminating potential damage to the equipment caused by multiple overcurrents, and providing an innovative solution for high-precision current protection.

Frequency standards play a vital role in modern science and technology and industry, in view of the problem of poor long-term stability of the constant temperature crystal oscillator affected by crystal aging and temperature and other factors, a constant temperature crystal oscillator frequency locking system based on phase-locked loop structure is designed, with the GPS signal received by the u-blox NEO-M8N module as the reference source, and the single-chip microcomputer STM32F103C8T6 as the control chip, and the frequency of the constant temperature crystal oscillator OC5SC25 is locked through the phase-locked loop structure. Using the extended Kalman filter and PID control algorithm, the long-term stability of the primary frequency standard and the short-term frequency accuracy of the secondary frequency standard are combined, and the test results show that the system realizes the frequency lock of the 10MHz constant temperature crystal oscillator, which can lock the frequency of the constant temperature crystal oscillator to a higher stability and accuracy. Its average frequency accuracy reaches 3.28×10^(-12), which is nearly 4 orders of magnitude higher than the initial frequency accuracy, which effectively improves the limitations of the constant temperature crystal oscillator in long-term stability.

Based on the current productization characteristics of Phase-Change Memory, this paper has conducted targeted research on four application scenarios in the SSD controller chip: ROM patch loading, abnormal log saving, power-off data preservation, storage of digital certificates，key update, etc. Storing ROM patches can save the ECO cost of the chip and reduce the production cost. Storing abnormal logs can well solve the backup of key information of logs and registers when the CPU is in abnormal state, greatly reducing the difficulty of problem location. Storing digital certificates and supporting key update ensure that sensitive information does not leave the main control chip, making it more secure and reliable. Supporting power-off data preservation greatly reduces the capacity requirement of the backup capacitor and lowers the cost of industrial products, making it possible for consumer-grade SSD to support abnormal power-off data preservation. Based on application requirements, a PCM controller was designed and implemented. Simulation results show that the designed PCM controller functions meet the design expectations. It can be seen that with the continuous improvement of PCM's read and write performance and lifespan, PCM has broad application prospects in solid-state storage and other fields in the future.

Addressing the resource constraints and energy efficiency bottlenecks in FPGA deployment of super-resolution networks, a lightweight hardware acceleration solution for the ESPCN super-resolution network is proposed. At the algorithm level, the ESPCN network is simplified to significantly reduce its computational complexity, and 16-bit fixed-point quantization is employed to further enhance computing efficiency. In the hardware architecture design, targeted optimizations are implemented for the hard-ware realization of standard convolution, pointwise convolution, and sub-pixel convolution. Experimental results indicate that the accelerator deployed on the ZYNQ7035 platform, operating at 210MHz, efficiently reconstructs a 480*270 resolution image to 1920*1080 resolution, with a forward inference time of only 49.8ms per image and a total on-chip power consumption of 4.17 W.

For application scenarios that require multi-channel high-speed acquisition and stable synchronization between channels, a multi-channel synchronous acquisition scheme based on Field-Programmable Gate Array (FPGA) is designed and implemented. This scheme uses FPGA as the control and processing core,employs high-speed Analog-to-Digital Converters (ADC) to build sampling channels,and designs a stable clock and synchronization scheme,thus realizing a multi-channel synchronous acquisition system under high sampling rates. The feature of this solution is that it can monitor and adjust the synchronization status among multiple channels in real time, and it can be conveniently extended to synchronous acquisition among boards. Through testing, it is found that each time the system is powered on and off, the collected data among various channels is in a stable synchronous state.

To meet the need of personalized talent training in Emerging Engineering Education, an experimental platform for moving object detection based on Python and embedded development board is designed. The platform combines advanced technologies such as edge computing, deep learning and image recognition to design experiment module. The experimental platform is configured based on the Linux system of the embedded development board. The moving target detection algorithms based on frame difference method, background subtraction and optical flow are developed using Python language. The deep learning algorithms are deployed based on Tencent ncnn computing framework to recognize the detected moving object. The platform enables students to choose different experimental projects and methods according to their interest in scientific research to improve the teaching effect.

High Definition Multimedia Interface (HDMI) technology is widely used in daily life.Therefore, the functional verification of the HDMI-CEC (Consumer Electronics Control) interface has become increasingly important. This paper designs and implements a verification platform for the HDMI-CEC interface based on the Universal Verification Methodology (UVM). The platform is capable of generating constrained random test excitations through its modular design, and the functional coverage and code cov-erage are used to evaluate the completeness of verification. The automated testing process and the coverage driven verification strategy of UVM are used in this paper, compared to traditional verification methods, significantly improving verification effi-ciency and accuracy. The core components of the verification platform are extended through UVM's standardized class library, ensuring the platform's reusability, scalability, and maintainability. The verification results show that the verification platform can effectively cover the various function points of the HDMI-CEC interface, so that the function coverage and code coverage are 100%, verify the validity and stability of the design. The research results of this paper provide an efficient and reliable solution for the verification of HDMI-CEC interface, offering significant engineering application value.

This paper proposes a spatial array-based processor core design where computing units communicate data via an interconnect bus and perform computations directly through local memory, eliminating the need for centralized register files. The processing results from local computing units are propagated to other units via a broadcast bus. This organization exhibits linear scalability, as the scale of computing units is not constrained by centralized components. It further incorporates flexible broadcast and reduction mechanisms that better align with algorithmic data communication patterns, facilitating efficient algorithm mapping and physical implementation. The processing element array implemented based on this design has high performance scalability, with a unit area performance of up to 1.4TOPS/mm2@INT8. It is suitable for large-scale deployment as a high computing power processor processing core.

With the development of semiconductor technology towards the deep sub-micron node, traditional synchronous circuits are facing increasing challenges in issues such as clock skew and high power consumption of the clock tree. Compared with traditional synchronous circuits, the asynchronous architecture, which uses a local handshake protocol to replace the global clock signal, is gradually becoming a new paradigm for high-performance computing chip design due to its modular design, lack of clock skew, and low-power consumption advantages.This paper focuses on the technological requirements for high-performance integrated circuit chips in future fields such as artificial intelligence and the Internet of Things. From the perspectives of the clock tree and the handshake protocol, it analyzes the limitations of synchronous circuits in large-scale integrated circuits, reviews the latest progress in asynchronous circuit technology, discusses the advantages and disadvantages of the handshake protocol in terms of operating speed, energy efficiency, and anti - interference, and prospects the next key research directions of asynchronous circuits.

Abstract:Aiming at the real-time performance degradation caused by frequent UART interrupts during high-volume data communication in embedded systems, this paper proposes a DMA driver optimization scheme for the FreeModbus protocol stack based on the GD32E230 microcontroller. By restructuring UART transmit/receive interrupt service routines and implementing DMA mechanisms, the solution significantly reduces UART interrupt frequency and CPU occupancy. Experimental results demonstrate that under 115200 baud rate, the interrupt triggers for 255-byte frame transmission decrease from 256 to 2 times, with a 99% reduction in CPU occupancy time. This optimization substantially alleviates system load, providing a cost-effective communication enhancement solution for resource-constrained embedded devices.

The demand for massive data processing such as artificial intelligence has greatly promoted the development of chiplet integration technology, which further puts forward technical requirements on FC-BGA substrates, including large size, low warpage, electrical performance and high reliability. The late-model glass core substrate has attracted extensive attention owing to its intrinsic low dielectric coefficient, high thermal stability and chemical inertness. This article overviews the history, characteristics, and present challenges of glass core substrate. It also provides a summary and prospect on the future application of glass core substrate in chiplet integration.

To improve the clock synchronization performance of the CT detector, a clock synchronization method based on a Time-to-Digital Converter (TDC) feedback mechanism and presents a complete prototype architecture of the synchronization system. For the first time, the TDC delay measurement technique based on carry chains is introduced into the clock synchronization scenario of CT detectors. A high-resolution delay measurement module is designed, incorporating multi-level comparators and high-precision delay elements to implement the timing scheduling logic. A finite state machine is employed to control the synchronization process, forming a closed-loop feedback synchronization mechanism. Simulation experiments demonstrate that in a complex scenario with 512 channels and a maximum transmission distance of 1.28 m, the system's synchronization precision can be stably maintained within 10 ps, improving by two orders of magnitude compared to traditional solutions. Even under conditions with interference-induced jitter, dynamic compensation can be applied to maintain the system's synchronization precision within 10 ps.

High-speed SerDes rates have progressed from 56Gbps to 112Gbps and beyond. Preserving signal integrity at these ultra-high speeds while balancing power consumption, reliability, flexibility, and cost-effectiveness is a hot topic in current research. The latest research progress in key technologies related to 112G SerDes is deeply explored from four aspects—transmitter, receiver, clock structure, and low-power techniques—based on the current mainstream architecture of analog-to-digital conversion and digital signal processing. This exploration is provided as a reference for research related to high-speed SerDes technology.