Based on HKN201 of Xiangteng Micro as the core, a strongly real-time, highly concurrent and high-performance edge-end embedded intelligent computing system has been constructed. Combining the design concept of high-speed circuits and practical engineering applications, the basic design methods and effective control measures for power integrity and signal integrity are provided, and simulation analysis is carried out with simulation results given. Finally, application tests are conducted on this system and performance indicators are presented. The experimental results show that this scheme has the characteristics of being universal, highly scalable and highly reliable, providing references for the research on intelligent products

With the shrinking of process nodes and the complexity of the three-dimensional structure of the device, the reliability of the device is becoming more and more important and has become an important issue of common concern in both academia and industry. In this paper, an in-depth study of the reliability of FinFET (Finned Field Effect Transistor) devices has been carried out, and ageing experiments have been designed and carried out under the conditions of different numbers of fins (Nfin), drain stress voltages (Vdstress), gate stress voltages (Vgstress) and temperatures (Temperature). Analysis of the test data shows that the ageing phenomenon of FinFET devices increases with increasing Nfin, Vdstress, Vgstress and temperature. Based on these experimental results, a reliability aging model is developed and parameter optimisation is used to achieve an effective fit to the degradation of threshold voltage (Vth_lin) and saturation current (Idsat). The model shows excellent simulation accuracy under different conditions, where the average simulation error of the threshold voltage is kept within 5 mV and the average simulation error of the saturation current is kept within 1%.

High-speed SerDes rates have progressed from 56Gbps to 112Gbps and beyond. Preserving signal integrity at these ultra-high speeds while balancing power consumption, reliability, flexibility, and cost-effectiveness is a hot topic in current research. The latest research progress in key technologies related to 112G SerDes is deeply explored from four aspects—transmitter, receiver, clock structure, and low-power techniques—based on the current mainstream architecture of analog-to-digital conversion and digital signal processing. This exploration is provided as a reference for research related to high-speed SerDes technology.

This article first introduces the three main requirements of a phase-locked loop (PLL) for Frequency Modulated Continuous Wave (FMCW) radar systems: frequency modulation bandwidth, frequency modulation slope, and linearity. Then, based on highly cited and influential articles from the past decade, it analyzes the advantages and application challenges of digital phase-locked loops (DPLL) in FMCW systems and briefly outlines the existing methods to overcome these challenges. The development trends of phase-locked loops in relation to the three main requirements are summarized, and a new figure of merit definition is proposed to evaluate the performance of PLLs for FMCW systems. Finally, it is pointed out that digital phase-locked loops are a key research direction for developing high-performance FMCW systems in the future.

In industrial control algorithms, the calculation of mathematical functions often requires a large number of clock cycles, affecting the performance of the algorithms. This paper conducts an in-depth analysis and comparison of related methods for calculating floating mathematical functions, and designs a piecewise table lookup polynomial fitting method based on the Remez algorithm, which is suitable for hardware circuit implementation to calculate mathematical functions. At the same time, the corresponding hardware circuits are implemented in the form of RISC-V custom instructions, closely coupled with the RISC-V processor core. Experimental results show that compared with no custom extension instructions, the processor's delay in calculating mathematical functions is reduced by 93.62%. Compared with the method of calculating mathematical functions using the CORDIC instruction set, the calculation delay is reduced by 79.83%. This achievement provides new ideas and solutions for low-cost, high real-time requirements of RISC-V architecture embedded microprocessors.

本文结合CCD图像传感器技术发展情况，基于CCD图像传感器高可靠应用需求，系统分析了CCD的产品特性，梳理了CCD主要失效模式，并深入研究了CCD由于静电损伤和辐照环境下的失效机理，并设计开展了典型试验验证工作，给出了不同辐照条件下失效变化曲线，为CCD高可靠评估和开展失效分析提供了理论依据和试验数据。为CCD产品高可靠应用提供技术指导。

This paper discusses a high-precision geomagnetic navigation algorithm based on interpolation matching and completes the hardware design and implementation of the algorithm. The geomagnetic navigation module relies on the spatial distribution characteristics of the geomagnetic field for positioning, but traditional algorithms are susceptible to noise and errors in complex environments, leading to insufficient positioning accuracy. To address this, the paper combines an interpolation matching algorithm to construct a refined geomagnetic intensity distribution model, enabling efficient processing and precise matching of geomagnetic field information. Additionally, a low-power, high-performance hardware architecture is designed to facilitate rapid execution of the algorithm. This design significantly improves the speed and energy efficiency of positioning calculations while maintaining high positioning accuracy in complex environments. It can be widely applied in modern navigation devices, providing an efficient geomagnetic navigation solution.

The Least Mean Square algorithm, as a typical adaptive filtering algorithm, has been widely used in the field of noise suppression, and its implementation is mainly based on general-purpose processors, which has the problem of low computational efficiency and performance.The RISC-V architecture, with the advantages of open-source, streamlining, and scalability, is suitable for the implementation of dedicated processors. In this paper, a RISC-V based specialized processor is designed for the LMS algorithm. The customized instruction set F extension is used to process floating point numbers, and MAC (Multiply Accumulate) instructions are added to the coprocessor to complete the acceleration of the LMS algorithm. Experimental studies show that the processor can realize effective noise cancellation, when the input signal-to-noise ratio is 5dB, the signal-to-noise ratio after noise cancellation is 17.5dB; The system uses FPU (Floating Point Unit) to execute the LMS algorithm, the number of instruction execution is 220354, and the execution cycle is 586221, and when this design scheme is used, working in FPU+MAC mode, the number of instruction execution is 31621, and the execution cycle is 89412, which improves the efficiency significantly.

To address the issue of caches being unable to predict nonlocal program execution and prepare for critical tasks, this paper proposes a high-security, first-level configurable instruction cache design. The design achieves flexible SRAM/Cache configurability through internal control registers. It ensures data access security for users at various levels through two granularity storage protection mechanisms: page-level and cache line-level. Rapid interaction with external storage data is achieved through direct memory access (DMA) to SRAM. A Universal Verification Methodology (UVM) verification platform is established to conduct module-level verification of the configurable instruction cache and collect coverage data. Different library functions are invoked to perform system-level verification and compare the hit rates of the cache under different L1P size configurations. A 40nm low-threshold library is utilized to conduct post-simulation verification of latency and power consumption. The results demonstrate that the designed cache can safely and swiftly switch between five L1P configurations of 32KB, 16KB, 8KB, 4KB, and 0KB during program execution, with a maximum path delay of 1.47ns and a total power consumption of 309.97mW, meeting the stable operation requirements of a 600MHz high-performance DSP.

With the rapid increase of data volume in today's era, higher requirements are put forward for data transmission technology, especially in terms of transmission speed, stability and reliability. When the traditional single channel LVDS data transmission system transmits for a long distance, its transmission rate is often only a few hundred Mbps, which is difficult to meet the requirements of high-speed data transmission. Therefore, this paper proposes a comprehensive optimization scheme: in terms of hardware, two groups of four channel LVDS chips are used as the high-speed interface of data, which realizes eight channel LVDS transmission and improves the data transmission rate; However, as the rate increases, the probability of error code generation under the effect of crosstalk and electromagnetic interference also increases. Therefore, it is necessary to cooperate with the anti-interference ability and long-distance transmission ability of LVDS dedicated data driver and cable equalizer system; In addition, RS encoding and decoding technology is introduced into the software logic to achieve error correction within a certain range. With automatic retransmission technology and CRC verification, the reliability of data transmission is improved. After many tests, the design can finally achieve 4000mb/s zero error transmission under 80m twisted pair shielded cable.