As a key technological pathway to break the limitations of traditional architectures and enhance overall computing power and system energy efficiency, emerging computing chip design is becoming a frontier direction attracting global attention from both academia and industry. By introducing innovative concepts such as memory-compute fusion, heterogeneous computing, neuromorphic computing, and hyperdimensional computing, researchers are actively exploring more flexible and efficient hardware solutions to further increase computational density, reduce energy consumption, and achieve stronger adaptability and intelligence. The continuous advancement of novel non-volatile memory technologies has laid a solid foundation for the deep integration of computation and storage. Additionally, specialized accelerators and optimized architectures tailored for emerging applications are continuously emerging, serving as critical enablers for key domains such as intelligent terminals, autonomous driving, and edge computing. High-bandwidth on-chip networks, data access optimization, flexible interconnect protocols, and efficient system-level integration solutions further provide robust support for the scalable application and multi-scenario deployment of emerging computing chips.

To facilitate the exchange and development of FPGA technology and showcase the latest research findings and application cases, this journal is launching a special issue titled "FPGA Frontiers and Application Research". Coverage includes innovative technologies in areas such as FPGA secure and agile design, EDA, domain-specific accelerators, heterogeneous computing, domestic FPGA applications, aiming to present the latest advancements in this field, foster academic exchange, promote sustainable innovation and development in this domain in China.

With the advent of collective longevity and an aging society, bio-medical research has become a globally focused priority in recent years and one of the most prolific fields for innovation. To address bio-medical application needs, core chips and chip-based system technologies are playing pivotal roles. From a scientific research perspective, customized chip designs enable functionalities unattainable by traditional bio-medical devices, thereby assisting researchers in acquiring richer biological data or delivering more effective interventions in organisms. For example, high-throughput, high-bandwidth brain-computer interface (BCI) chips allow dense monitoring and modulation of neural tissues across extensive brain regions, deepening our understanding of the brain. From a practical application standpoint, highly integrated chip designs miniaturize traditionally bulky medical equipment, enabling wearable or minimally invasive implantable devices—such as smartwatch, fitness tracker, and continuous glucose monitor (CGM) gaining popularity in recent years. China’s bio-medical device market has reached hundreds of billions of USD, yet most high-end equipment remains import-dependent, with a critically low localization rate for core chips. Therefore, achieving self-reliance in biomedical chip R&D is essential for securing supply chains and advancing industrial upgrading. However, designing biomedical chips faces major challenges: Extreme reliability requirements (especially for implantable medical devices), where human safety demands rigorous chip robustness; high interdisciplinary complexity—spanning fields including but not limited to bio-medicine and integrated circuits—entails substantial investment, slow returns, and costly iterations; prolonged development cycles due to stringent performance standards and regulatory certifications, significantly delaying hardware deployment (particularly for core chip upgrades). To address these cross-disciplinary challenges, this journal presents the "Special Section: Bio-Medical Chips and Systems Research".

Driven by increasing complexity and scale of space missions, reliability requirements for space-grade components have escalated significantly. At the design stage, leveraging advanced simulation and modeling technologies to proactively predict and avoid potential failure risks has become a critical technical challenge. Concurrently, integrating intelligent solutions—such as embedded micro-sensors and AI-driven algorithms—for real-time component health monitoring and predictive diagnostics has emerged as a pivotal research frontier. Furthermore, the expanding adoption of technologies such as artificial intelligence, big data analytics, and cloud computing in aerospace applications substantially enhances the intelligence and performance of space-grade components, playing an indispensable role in reliability research.

Driven by rapid advances in robotics and artificial intelligence, intelligent robots are emerging as revolutionary engines propelling next-generation productivity and spearheading a new global wave of technological transformation. Intelligent Robotics possesses capabilities spanning environmental perception, real-time analysis, autonomous decision-making, and self-adaptive learning—all fundamentally reliant on master control chips that serve as core computing platforms delivering formidable computational power. Consequently, intelligent robotics master control chips have become critical enablers determining robotic functionality and performance benchmarks.

With the continuous advancement in intelligence of mobile robots, the complex tasks performed by robots—including perception, localization, mapping, navigation, interaction and so on—pose two critical challenges to the computational power and energy efficiency of master control chips. On one hand, these complex tasks require processing massive amounts of sensor data and frequent memory access, demanding high computational power for real-time processing and rapid response. On the other hand, high computational power leads to elevated energy consumption and battery limitations under mobile operating conditions, requiring chips to enhance energy efficiency while maintaining computational performance to extend operational endurance.

Application-specific computing chips, designed and optimized for dedicated algorithms, tasks, and requirements, represent a critical pathway to addressing the dual challenges of computational power and energy efficiency. Developing energy-efficient application-specific integrated circuits (ASIC) for intelligent mobile robots—particularly space-constrained and energy-limited small-scale, micro-, and nano-robots—is imperative, emerging as a pivotal research trend in the field.

Integrated circuits have been extensively deployed across critical sectors including industrial production, transportation, mobile communications, and financial payment systems, forming a foundational pillar of China's information infrastructure and national security framework. Typical IC designs now integrate dozens of IP cores, millions of lines of HDL code, and hundreds of millions of transistors. With development spanning design, fabrication, testing, and packaging phases, vulnerabilities may be introduced at any stage. Attackers can exploit these hardware flaws to compromise sensitive data, disrupt operations, or sabotage entire systems—rendering IC hardware security a critically heightened concern.

As the cornerstone of information technology, integrated circuits underpin the development of strategic emerging industries and propel the new wave of technological transformation and industrial advancement. Reliability—a comprehensive discipline spanning materials science, electronics, thermal dynamics, and mechanics—serves as a critical metric for product quality evaluation. To provide readers with in-depth insights into IC reliability developments, this journal presents the "Special Section: Reliability Research for Integrated Circuits". This section focuses on IC reliability design, verification methodologies, simulation technologies, and failure mechanism modeling. These cutting-edge theories and techniques consolidate the latest research achievements from leading experts, offering vital academic perspectives on the trajectory of IC reliability technology.

Visual information accounts for over 80% of the total information acquired by humans, and image sensors serve as the primary means for humans to obtain visual information. Among various types of image sensors, silicon-based CMOS image sensors are currently the most widely used. They are fundamental devices for building an information society and play a vital role in the national economy and social life. CMOS image sensors are a category of integrated circuit chips fabricated based on CMOS processes. The chip monolithically integrates photosensitive devices (pixel arrays), photocurrent readout circuits, data output interfaces and on-chip image processing units, while also incorporating micro-optical components such as microlens arrays and spectral filters, representing a quintessential optoelectronically converged integrated circuit.

Space-grade integrated circuit technology stands as a mission-critical enabler for achieving miniaturization, integration and intelligence in aerospace systems. Its advancement holds profound significance for enhancing national space capabilities and safeguarding security worldwide. Distinct from commercial IC technologies, space-grade IC prioritizes extreme reliability, extended lifespan and resilience in harsh orbital environments.Therefore, it exhibits specific characteristics in design, fabrication, packaging, testing, application and so on. It is necessary to study both common specialized technologies represented by radiation-hardened reinforcement and high-reliability packaging, as well as key technologies for the development of different types of products.

To address the issues of yield degradation and increased cost in advanced process nodes for very-large-scale integration, chiplet technology divides a large monolithic chip into multiple smaller chiplets. Each chiplet is manufactured independently, enabling better control over the fabrication process, improving yield and reducing cost. In addition, different chiplets can be fabricated using the most optimal process technologies, overcoming the limitations of a single process node. This also enhances the reusability of intellectual property cores and shortens the research and development cycle. Various types of chiplets can be integrated into a single chip, and developing an optimal chiplet partitioning and integration methodology based on target applications is a significant technical challenge. The partitioning of chiplets must take into account factors such as the performance, cost and security of the integrated chip.The combination of chiplets is a complex optimization problem that involves selecting the optimal chiplets from an existing chiplet library based on application requirements.

IC EDA tools are not a single tool, but a cluster of point tools, forming a toolchain from front-end design (from RTL to gate-level netlist) to back-end design (from gate-level netlist to GDS). This toolchain includes synthesis, simulation, floorplanning, placement and routing, timing and power analysis and optimization, etc. Breakthroughs in EDA tools depend, on the one hand, on key technological breakthroughs in each EDA point tool, and on the other hand, on the integrated design optimization of these point tools. Therefore, the chaining of EDA point tools based on a common data infrastructure and the integrated optimization based on the full EDA chain have become the inevitable path to drive breakthroughs in EDA tools.

Next-generation embedded intelligent systems have an increasing demand for high-performance computing. While meeting the requirements of high computing power and strong real-time performance, adopting heterogeneous multi-core intelligent chips in hardware and deploying mixed-criticality systems in software is becoming one of the trends in the evolution of embedded technology. Currently, mixed-criticality systems based on heterogeneous multi-core intelligent chips have seen some typical applications in fields such as autonomous driving, service robots and automotive electronics, and are showing a positive development trend in fields such as industry and national defense.