Neural Radiance Fields (NeRF) is an emerging method for reconstructing 3D scenes, garnering significant attention for its potential applications in the field of robotics. NeRF uses Multi-Layer Perceptrons (MLPs) to learn 3D scene features, achieving high-fidelity image rendering and providing a foundation for navigation, localization, and perception in complex environments. Its core processes, including ray sampling, feature extraction, and volumetric rendering, are computationally intensive and involve irregular memory access patterns, which limits deployment on existing hardware platforms, especially edge devices. To advance the practical application of NeRF technology, new hardware architectures and solutions for co-optimization of hardware and software are necessary. This review systematically elucidates the principles and evolution of NeRF technology, exploring the performance bottlenecks encountered during its hardware execution. The review provides a detailed review of classic NeRF hardware accelerators, summarizing three main optimization directions: image similarity optimization, spatial sparsity optimization, and memory access optimization, and analyzes the commonalities and differences among various techniques. Additionally, the review examines the technical limitations and challenges of current NeRF accelerators in handling open scene tasks, considering applications such as SLAM and AIGC, particularly in terms of scalability and storage constraints. Finally, the review offers suggestions for future development to inspire further applications and optimization of NeRF hardware accelerators.

Chiplet integrates multiple small chips into a system chip,aiming to achieve various goals such as chip reusability,heterogeneous integration,performance enhancement,and cost reduction.The development trends of the Chiplet primarily encompass heterogeneous integration,innovative interconnects,and advanced packaging.Notably,interface interconnection is the key of Chiplet technology.Interconnection using the design of physical layer interfaces and data transmission protocols,considering factors like process,packaging techniques,power constraints,and requirements of upper-level applications.Serial and parallel interconnects are two choices for chip-to-chip physical layer interfaces,each with its own advantages and application scenarios.Additionally,for different propagation media,emerging interconnect technologies such as optical and wireless interconnects offer higher bandwidth,lower power consumption,and more flexible interconnection topologies.Chiplet is promising to bring significant breakthroughs and advancements to the field of electronics,promoting more efficient,flexible,and innovative chip design and manufacturing.

Single-photon imaging technology involves multiple aspects such as semiconductor processes,optoelectronic devices,and integrated circuit design.Based on single-photon avalanche diodes,single-photon imaging technology offers high dynamic two-dimensional grayscale imaging,high-precision three-dimensional imaging,and fluorescence lifetime imaging capabilities.It has significant application prospects in fields such as security surveillance,autonomous driving,and biomedicine.With the rapid development of semiconductor process technology,single-photon imaging technology is expected to become a widely used next-generation visual perception technology.This article provides a systematic introduction to imaging technology based on single-photon avalanche diodes,including the device structure of single-photon avalanche diodes,key circuits involved in single-photon imaging,and the latest research progress in gray scale and temporal resolution single-photon image sensors.

Aerospace integrated circuits are the core foundation technology of aerospace engineering,and their long-term sustained development is crucial for China's progress towards becoming a space power.This article introduces the development status of international integrated circuits,the development trends of aerospace integrated circuits,the development strategies of United States and Europe regarding aerospace integrated circuits,as well as the current development situation of China's aerospace integrated circuits.It elaborates on several considerations for the development of China's aerospace integrated circuits.

In the paper,an open source smart home project is introduced,and realizes the control of DALI(Digital Addressable Lighting Interface) lamps by HOMEASSISTANT through a DALI gateway and custom components of HOMEASSISTANT. Various lighting effects are achieved in the home.

A single-event burnout (SEB) hardened design based on N-type lateral double-diffused metal-oxide-silicon (NLDMOS) devices with a Nbuffer layer is proposed in this paper.The electrical and single-event characteristics of NLDMOS is verified by TCAD simulation.Without changing the device performance,the 18 V NLDMOS SEB trigger voltage increases from 22 V to 32 V,reaching the theoretical maximum,which is the avalanche breakdown voltage of the device.The NLDMOS device with an Nbuffer structure can suppress the peak electric field transfer when the parasitic bipolar transistor is turned on due to single paricle incident,and avoid avalanche breakdown of the device causing SEB.Furthermore,Nbuffer is also suitable for SEB hardening of 18~60 V NLDMOS.

In the flight test,in order to solve the problems of low data transmission rate,insufficient transmission distance and poor transmission reliability during data communication between ground test equipment and remote equipment,a "gigabit ethernet + optical transceiver integrated module" long-distance transmission design is proposed based on ZYNQ.This design uses Xilinx's ZYNQ7000 series XC7Z015 as the main control chip,the PS side realizes data interaction with the host computer through the TCP protocol,and the PL side realizes the UDP protocol communication with the telemetry equipment by calling Xilinx's three-speed Ethernet IP core.In the process of Ethernet receiving data,a request retransmission mechanism is designed to ensure the reliable transmission of data.Secondly,an integrated optical transceiver module is added,and the optical cable is used instead of the cable,and the signal transmission distance is increased by the conversion of the electrical signal and the optical signal.It has been verified that the data transmission rate can reach 669 Mb/s under the condition that the system and the remote equipment are connected by a 20 km optical cable,and there is no error or frame loss during the data transmission process,and the operation is stable.

As the size of semiconductor technology gradually approaches the physical limit,the progress of process technology has led to a decreasing improvement in the power consumption,area,and other performance of chips,semiconductor technology has entered the “post-Moore era”.In order to further meet the high bandwidth communication needs brought about by the rapid development of machine learning,artificial intelligence,and other information and communication industries,Chiplet technology which based on advanced interconnection and packaging techniques,steps into the picture.Chiplet technology disassembles the original complex multifunctional SoC chip into small chips with small area,low cost,and different process nodes,and assembles them through advanced packaging technology,which has received high attention from academia and industry due to its advantages of high yield,low cost,high integration,strong performance,good flexibility,and fast time-to-market.This paper summarizes and elaborates on the technical characteristics,advantages,development history,and specific applications of Chiplet.Meanwhile,the core technologies of Chiplet,especially Chiplet D2D interconnect technology,are introduced in detail.Finally,the existing technical issues and challenges of Chiplet are described,and the suggestions for future development are put forward.

Based on the RISCV standard instruction set,a six-stage pipeline design is designed in the paper.First of all,this article analyzes the impact of pipeline stages on processor performance,and divides the pipeline into six-stage on the basis of the classic five-stage pipeline,reducing the delay to improve the main frequency.Secondly,in order to solve the risk problem in the pipeline,this design adopts the method of pushing forward and inserting longitudinal bubbles to deal with the data adventure problem,and uses the pipeline flushing to solve the control risk problem in the pipeline.Finally,in the EDA tool,the design is simulated using the RISCV standard instruction set and implemented on the FPGA,running at clock frequencies up to 78.2 MHz.

Miniaturization of chip/system dimensions and functional composites have led to an increase in power density, accompanied by the growth in heat generation. Addressing this problem has become a great challenge in thermal design and a current research hotspot. This paper discusses the advantages and disadvantages of traditional heat dissipation techniques, and systematically analyzes the embedded microchannel heat dissipation structures at home and abroad. The article focuses on summarizing the principles, thermal performance and innovative solutions of heat dissipation technology based on embedded microchannel chips. Current domestic and international solutions are analyzed, and we summarize the experiences and conclusions of chip thermal design based on embedded microchannels, along with the challenges faced. Finally, the current status and future directions of chip thermal design research are presented.

To evaluate the single event effects vulnerability of electronic systems being used in space environment,and verify the effectiveness of system-level hardening methods against radiation,this article conducts relevant research on system level single event effect testing methods.Feasibility of irradiating devices in electronic systems one by one under laboratory environment to evaluate single event functional interrupt rate is confirmed.It is suggested that many methods could be used to get the vulnerability data of devices.The procedure to directly sum up the cross section value corresponding to each device is pointed out to be not reasonable.Through all the above suggestions,it is able to support the test for system-level single event effects.

High-level synthesis (HLS) tools are becoming popular in some applications such as digital signal processing and neural network,but their usability for cryptographic applications is largely unexplored.SM4 algorithms have been widely used in data encryption with increasing performance requirements for the widely used SM4 algorithm,which have the advantages of strong security,high efficiency and easy hardware implementation,and the use of hardware features for high-speed.The implementation of SM4 algorithm has become a hot topic of current research.In this paper,we use high-level synthesis(HLS) tools to synthesize C into the underlying hardware design,and propose three optimization schemes: loop unfolding,array optimization,and pipeline optimization to implement and optimize the SM4 algorithm hardware implementation.The design solutions are simulated and verified on Kintex-7 chip,and the best solution achieves a clock frequency of up to 223 MHz and a throughput of 32.10 Gb/s,which is a five-fold performance improvement over the traditional design approach.

In the paper,the definition,advantages and current problems of tiny machine learning are introduced.From exclusive or general tiny machine learning deployment methods,microprocessor design based on ARM Cortex-M or RISC-V,and deployment algorithms based on neural architecture search,the existing problems are discussed and the research status is introduced.Looking forward to the future development of tiny machine learning,it is believed that a full-featured tiny machine learning deployment framework is needed in the future,and hardware research is more based on RISC-V and hardware neural network acceleration units to form microprocessors,and how to improve search efficiency and reduce neural architecture search time.Finally,on the basis of the above,some thoughts are put forward on how to improve and develop the tiny machine learning ecology.

To further optimize the performance of the multiplier and improve the operation speed of the multiplication unit,an improved 16-bit signed number multiplier is designed based on the Radix-4 Booth algorithm and Wallace tree compression structure.Its characteristics are:optimize the Radix-4 Booth encoding method to effectively reduce the area of partial product selection circuits.Improve the partial product calculation process by optimizing the inverse plus one method to directly generate the opposite of the multiplicand,at the same time,use the classic sign bit compensation algorithm to make the partial product array regular and easy to compress.A new type of 4-2 compressor is proposed,which uses a single full adder to process the middle carry of the compressor.The Wallace tree compression structure is refined to improve the compression efficiency of partial products for different data features in each row.Synthesis and verified based on SMIC 180 nm standard cell library,the results show that the critical path delay of the multiplier designed in this paper is 3.94 ns,with an area of 16 246 μm².Compared to existing multipliers,the computational speed and overall performance of the multiplier in this paper have been significantly improved.

Facing the challenge of the "area wall" in chip design,there is a significant increase in chip manufacturing costs.The chiplet technology enables the production of small area chips using a mature process,and composing by advanced packaging techniques,which can overcome the limitations imposed by the area wall,facilitating agile chip design and reducing overall design costs.Determining an optimal chiplet particle size to meet flexible chip design requirements remains a crucial issue when utilizing chiplet technology.Furthermore,achieving interconnectivity between functional chiplets after dividing chip functions is pivotal for realizing the final functionality of the chip.Therefore,this paper provides a comprehensive review of recent research on chiplet function division,spatial exploration in chiplet design and the influence of chiplet function division on the inter-chip interconnect,while also pointing out that chipet design methodology is an important research direction for the development of chiplet technology in the future.

Computing-in Memory (CIM) is an emerging architecture to alleviate "memory walls" and "power consumption walls".With further expansion of the imbalance between CPU processing speed and memory access speed,structures that separate the central process and memory,such as the Von Neumann architecture,lose its superiority.CIM proposes a novel structure that combines the compute unit and the storage to reduce data movement,significantly improving computational efficiency.MRAM,as one of the most promising next-generation nonvolatile memory devices,is also considered a strong candidate for building efficient CIM architectures.CIM based on MRAM can be divided into analog MRAM CIM and digital MRAM CIM according to the different calculation processes.Digital MRAM CIM can be further divided into MRAM write-type CIM,MRAM read-type CIM,and MRAM near memory computing (MRAM NMC) based on how digital logic is generated.Analog MRAM CIM utilizes high parallelism to amortize energy consumption,which has unparalleled advantages in throughput and energy efficiency per unit area compared to digital CIM.However,It is also limited due to its susceptibility to PVT and other characteristics.The implementation methods of digital MRAM CIM are diverse,and write-type CIM almost eliminates data movement outside the memory.Although the flip energy consumption and delay required by the current process of MRAM are too large,which leads to this method staying in the simulation,it does not hinder that write-type CIM is one of the most effective means to alleviate the "memory wall".Read-type CIM relies on the functional design of read amplifiers which has severe limitations,but there still have some developments in the related field.NMC method is an optimal solution that combines the advantages of MRAM nonvolatile devices and CMOS circuits,though there are significant differences in speed and computational energy efficiency between this two devices,and has achieved significant benefits in practical applications.

The combination of Robots and artificial intelligence will lead the transformation of new intelligent technologies. Furthermore, as a crucial component of artificial intelligence, neural networks demonstrate immense potential in robotic perception. However, the increasing complexity of AI algorithms and the prominent energy efficiency bottleneck of general-purpose processors such as CPUs pose significant challenges. Traditional processing chips fail to effectively accommodate the inference computing tasks of large-scale neural networks. In recent years, robotic AI chips, with high computing performance and low power consumption, have emerged as an ideal choice for deploying of neural networks in robot systems due to their, attracting widespread attention. This article focusing on robotic applications, studies the current status of AI algorithms, reviews the latest advances in AI chip design technology, proposes technical difficulties and feasible technical routes, and discusses the technical trends and challenges in the design of robotic AI chips.

The reliability of ULSI/VLSI integrated circuit chips is related to both design and process. In order to make the chip of ULSI/VLSI operate stably during a specific lifetime, it is necessary to evaluate the inherent failure mechanism that affects the reliability of chips. The purpose of the evaluation is to determine the mechanism of technical wear and ensure that the chip has good reliability throughout the product life by improving the design and process processing level. This paper reviews the reliability evaluation standards of inherent failure mechanisms at home and abroad, expounds these inherent mechanisms, summarizes the experiment methods of different inherent failure mechanisms, and puts forward the reliability evaluation requirements of inherent failure mechanisms. The reliability evaluation of failure mechanisms play a role in process development, library construction and engineering services, and will promote the development of domestic qualitied manufacturer certification.