Based on the RISCV standard instruction set,a six-stage pipeline design is designed in the paper.First of all,this article analyzes the impact of pipeline stages on processor performance,and divides the pipeline into six-stage on the basis of the classic five-stage pipeline,reducing the delay to improve the main frequency.Secondly,in order to solve the risk problem in the pipeline,this design adopts the method of pushing forward and inserting longitudinal bubbles to deal with the data adventure problem,and uses the pipeline flushing to solve the control risk problem in the pipeline.Finally,in the EDA tool,the design is simulated using the RISCV standard instruction set and implemented on the FPGA,running at clock frequencies up to 78.2 MHz.
Key words
RISCV /
processor architecture /
pipeline /
data hazards
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