Chiplet systems integrate multiple chiplets that are independently designed, manufactured, and tested, providing an important pathway for high-performance computing in the post-Moore era. However, emerging Chiplet-based architectures reshape the hardware security boundaries of conventional monolithic systems-on-chip (SoC) and introduce new requirements for security testing. This paper reviews research on hardware security threats, defense mechanisms, testing, and verification for Chiplet systems. It analyzes the applicability of existing SoC security testing techniques to Chiplet scenarios, summarizes emerging testing requirements, and proposes a Chiplet lifecycle security testing and verification process for compositional trust. The potential security risks introduced by test infrastructures are also examined, followed by a discussion of major research directions and key challenges.
As CMOS technology nodes continue to scale down, aging effects such as Negative Bias Temperature Instability (NBTI) have become increasingly significant and have emerged as critical factors affecting circuit reliability. Accurate prediction of the aging-induced performance degradation in integrated circuits can mitigate the risk of in-field failures. A promising prediction paradigm involves the continuous collection of chip operating conditions, including supply voltage, temperature, signal duty cycle, and partial performance-degradation information, and constructing a machine-learning model that uses past degradation observations to forecast future degradation trends. Such a capability aligns closely with the objectives of Silicon Lifecycle Management (SLM), which seeks to monitor, analyze, and optimize chip performance throughout its operational lifetime. In this paper, we propose the Conditional Autoregressive Transformer (CAT), a decoder-only sequential prediction model that, conditioned on chip operating conditions and historical degradation traces, predicts the degradation trajectory over a future time horizon. CAT leverages causal attention mechanisms to capture the temporal dependencies inherent in NBTI aging dynamics, enabling multi-step extrapolation from partial sensor data. Experimental results demonstrate that CAT achieves accurate degradation forecasting, offering a practical solution for SLM-driven reliability management in advanced CMOS technologies.
Clustering defects in die-to-die interconnect architectures of three-dimensional storage systems constitute one of the critical factors affecting system reliability. To address this challenge, this paper proposes a real-time diagnostic method based on spatio-temporal error information from on-chip error-correcting codes (OD-ECC). The proposed method leverages error location information from multiple consecutive data reads to identify fault patterns, and innovatively incorporates ECC syndrome as an additional criterion to effectively distinguish between fixed faults induced by clustering defects and random soft errors. In this work, we establish a mathematical model for die-to-die interconnect arrays and clustering defects, derive analytical expressions for recall and precision under varying decision thresholds, and construct a Monte Carlo simulation platform for verification. Simulation results demonstrate that, under conditions of a random error probability p=10-4 and k = 12 consecutive reads, the proposed method achieves recall rates of 98.97% and 96.24% for 1×2 and 2×2 clustering defects, respectively, with precision rates of 99.74% and 99.16%, respectively—significantly outperforming baseline diagnostic methods that rely solely on location information. By incurring only a marginal loss in accuracy, this approach substantially enhances the detection capability for clustering defects, thereby providing robust support for the reliability design of three-dimensional storage systems.
This paper presents the design and extensive wide-temperature characterization of a 10-bit, 1 GSa/s, 8-channel time-interleaved successive approximation register (TI-SAR) ADC fabricated in a 55 nm CMOS process. The converter employs eight asynchronous SAR sub-ADCs and integrates local reference buffering, SRAM and SPI-based data transfer, off-chip mismatch estimation, and on-chip adjustable sampling delay correction. The prototype is evaluated over a wide temperature range using low-frequency and near-Nyquist input tones. The measurement results are analyzed in terms of effective number of bits (ENOB), signal-to-noise ratio (SNR), harmonic distortion, and residual spectral components associated with interleaving. Measurement results show that the ADC achieves an ENOB of 6.37~6.79 bits over the measured temperature range. As the temperature increases from -25 ℃ to 95 ℃, the SNR decreases by 1.35 dB and 1.71 dB for 49.987 8 MHz and 450.012 2 MHz input tones, respectively, with a total power consumption of 22.36 mW. A complete high-temperature calibration record is further used to verify that the timing correction path remains functional under the most severe measured condition. Normalized error-power analysis shows that the high-temperature degradation is mainly associated with increased residual background error rather than deterioration of calibrated interleaving mismatch. These results support wide-temperature robustness evaluation and residual-error diagnosis of TI-ADCs.
Currently, the number of test channels in automated test equipment (ATE) limits the number of integrated circuits (ICs) that can be tested in a single session. This paper proposes a capacitive-coupled architecture for multi-IC parallel wireless testing based on capacitive coupling. The architecture couples signals from the capacitive plates on the test board to the capacitive plates at the bottom of the ICs. The signals are transmitted via through-silicon vias (TSVs) to the test circuits in the interposer layer. By using the System Information Block (SIB) to control the signal path into the chiplets, capacitive coupling enables wireless transmission of test signals. Simulation experiments are conducted to verify the feasibility of the proposed method. The results show that this method can demonstrate feasibility parallel wireless testing for a potential parallel testing capability and can transmit wireless test signals at a speed of 119.21 MB/s.
With the rapid development of large-scale artificial intelligence models, hyperscale data centers, and high-performance computing, system interconnects are evolving toward higher data rates, higher bandwidth density, and lower power consumption. Silicon photonic integrated circuits (SiPh PICs), benefiting from CMOS-compatible fabrication, high integration density, and low power consumption, have become an important technology platform for high-speed optical interconnects and co-packaged optics (CPO) optical engines. However, efficient and repeatable fiber-to-chip coupling remains a key challenge in wafer-level testing, packaging integration, and CPO optical engine verification. This is mainly attributed to the significant mode-field mismatch between standard single-mode fibers and silicon waveguides. In addition, facet reflection, refractive-index discontinuity, and alignment errors may introduce extra optical loss and affect measurement accuracy. This paper reviews wafer-level fiber coupling technologies for SiPh PICs. First, the architecture, testing workflow, and main error sources of automated coupling systems are introduced. Then, grating coupling and edge coupling are analyzed in terms of operating principles, typical structures, and performance characteristics. Furthermore, coupling devices such as single-mode fibers, lensed fibers, fiber arrays, and emerging optical probes are discussed, together with active alignment, passive alignment, and automated coupling control algorithms. Finally, future trends are summarized, including low-loss coupling, high alignment tolerance, multi-channel parallel testing, automated optimization, and data-driven feedback. This review provides a reference for wafer-level SiPh PIC testing platforms, fiber-array packaging, and CPO optical engine integration and verification.
Yield learning and failure analysis often begin with a small set of sites confirmed by scanning electron microscopy (SEM) or electrical analysis. This work presents R2-Layout, a known-defect-driven multi-instance retrieval system that expands physical review from one confirmed site to structurally similar layout regions. R2-Layout combines structure-aware detector descriptor learning, rotation and reflection augmentation, a template-guided candidate heatmap, and local geometric verification. On a controlled benchmark comprising 50 stitched layouts and 400 ground-truth instances, it achieves a center-hit precision of 0.962 6, a center-hit recall of 0.965 0, and an IoU@0.1 recall of 0.970 0. Furthermore, on 300 random queries across six OpenROAD realistic routed-design layouts, center-hit recall and IoU@0.1 recall reach 0.970 0 and 0.973 3 respectively, demonstrating stable query repositioning under complex routed back- grounds. In a real failure analysis case, a layout context around one SEM confirmed bridge defect is used to search 500 μm windows from different dies on the same wafer. Three additional sites are returned for review, and subsequent SEM examination identifies a morphologically similar bridge defect at one site. The case demonstrates an engineering loop from defect localization to similar structure expansion and physical confirmation. Layout similarity is used only for candidate discovery and is not interpreted as a defect label or causal conclusion.
To address shrinking performance margins in high-speed PCIe interfaces for AI computing chips, this study uses a TPU PCIe Gen5 link as a representative case to establish a four-dimensional stress model encompassing channel loss, jitter, power-supply noise, and transmit equalization. An automated test platform is developed, and Design of Experiments (DoE) together with Analysis of Variance (ANOVA) is applied to enable systematic margin characterization and performance boundary identification. Through measurement and analysis on a TPU PCIe Gen5 link, the results demonstrate that channel loss is the primary bottleneck affecting eye closure, with a contribution of 42%. The loss-jitter interaction contributes 18.7%, revealing the critical vulnerability of significantly amplified jitter sensitivity under high-loss conditions. The BER=1E-12 performance boundary map, derived from the full-factorial experiment, identifies three failure regions that remain undetected by conventional single-variable testing. This methodology achieves a paradigm shift from binary "pass/fail" assessment to quantitative margin analysis, providing a quantitative foundation for the robust design and reliability assessment of high-speed interfaces in AI computing chips.
As CMOS technology scales to the 55 nm node, the concomitant thinning of the gate oxide has made Time-Dependent Dielectric Breakdown (TDDB) a key mechanism limiting chip reliability. The appropriate model for gate oxide TDDB lifetime projection—whether the E-model, 1/E-model, Power-law model, or $\sqrt{\mathrm{E}}$-model—remains a contentious issue, as extrapolations can differ by several orders of magnitude, thereby compromising the accuracy of lifetime assessments. This study systematically evaluates these four mainstream acceleration models using TDDB data from a 55nm process, comparing their goodness-of-fit across distinct stress regimes: a high-voltage region (2.7~2.85 V) and a low-voltage region (2.55~2.7 V). Our analysis reveals that while all models provide a reasonable fit to their respective data, their applicability is strongly dependent on the voltage regime. The E-model provides the optimal fit in the high-voltage region (R2=0.996 6), where the 1/E-model performs poorly (R2=0.994 5). In contrast, the 1/E-model demonstrates the highest fidelity in the low-voltage region (R2=0.991), where the E-model is least suitable (R2=0.987 9). The Power-law and $\sqrt{\mathrm{E}}$ models exhibit intermediate performance in both regimes. These findings indicate that no single model is universally applicable, instead, model selection must be based on the relationship between the stress conditions and the intended operating voltage. By contextualizing these results within the frameworks of percolation theory, the thermochemical model, and the anode hole injection model, this paper reveals the physical applicability boundaries of each model. Finally, leveraging the optimal model from the high-stress data, we extrapolate the characteristic lifetime of the 55 nm gate oxide at its nominal operating voltage. These research findings provide critical experimental evidence to guide model selection for TDDB lifetime assessment in advanced process nodes and hold significant practical value for robust reliability engineering.
