To assist visually impaired individuals in navigation, an AI-based machine vision system for collecting tactile paving information has been designed to enable intelligent data acquisition. The system ide.pngies standard tactile paving through image edge detection and morphological constraints, enabling wheeled robots to autonomously traverse tactile paths. It employs the YOLOv8 object detection model paired with Huawei Ascend AI processors to detect anomalies in tactile paving, transmitting detection results to a host computer via Wi-Fi. Experiments were conducted on a simulated tactile paving testbed composed of 30 cm×30 cm tiles, including damaged tiles, missing sections, and movable and immovable obstacles at different locations. Multiple detection runs were conducted with damaged tactile paving, missing sections, and both movable and immovable obstacles placed at various positions. Testing confirmed the system̓s capability to collect tactile paving data within defined scenarios, ide.pngy anomaly types and locations, with an average detection accuracy of 95%. The average absolute error in anomaly location pinpointing was less than 9.12 cm relative to actual positions. The proposed system provides technical support for tactile paving inspection, maintenance management, and accessible mobility assistance for visually impaired individuals.
Aiming at the problem that the existing FPGA matrix inversion methods are difficult to balance hardware resources, calculation delay and calculation accuracy, this paper proposes a matrix inversion architecture that integrates algorithm optimization and hardware architecture design. In this paper, based on MGS-QR decomposition, the parallel vector operations in the operation flow are integrated, and the calculation of the inverse matrix is transformed into the integration of the partial sum of each iteration in the iterative process, and the vector processing unit adaptation algorithm supporting multiple vector operation modes is designed. This architecture enables N×N real matrix inversion with resource consumption scaling quadratically and clock cycles scaling linearly with the matrix size. It can therefore accommodate matrices of different sizes. Compared with the traditional MGS-QR factorization matrix inversion method, the designed architecture further reduces the amount of DSP usage and significantly lowers the calculation delay under the premise of ensuring the same calculation accuracy, which can provide an efficient and highly reliable engineering solution for real-time matrix inversion in embedded systems.
In compute-in-memory (CIM) employing high-density 2T0C arrays, parasitic capacitances critically determine charge redistribution and bit line integration dynamics, directly impacting storage-node (SN) disturbance and computational linearity. However, the escalating computational cost of conventional extraction methods with array size obstructs efficient array-level modeling and system analysis. To address this, we propose a high-accuracy approximation method for extracting parasitics from the central cell of large-scale arrays by leveraging the attenuating coupling of long interconnects. The method constructs a nine-port aggregated equivalent network by bundling non-adjacent word/bit lines and derives a quantitative expression for the minimum truncation distance of key capacitances under a 1% relative-error bound, enabling rapid array-level (AM) parameter extraction. This facilitates high-accuracy models for the SN and bit line capacitances (CSN and CRBL) across operational phases, accurately capturing the near-linear scaling of CRBL with array size. Simulations under 10× geometric scaling show a 15% accuracy improvement over the device-level model (DM). Crucially, linearity analysis based on this precise model reveals that using the low-accuracy DM would overestimate the peak integral non-linearity (INL) by approximately 1.5 least significant bit (LSB).
With the rapid development of edge A.pngicial Intelligence (AI) technologies, resource-constrained terminals impose increasingly stringent requirements on the energy efficiency of neural network inference. However, existing multi-bit neural network models and their hardware implementations generally suffer from high power consumption and complex architectures, which limit their applicability in low-power scenarios. Therefore, this work focuses on the demand for lightweight inference in edge vision tasks and proposes a low-power computing-in-memory (CIM) circuit design for convolutional inference based on Binarized Neural Networks (BNNs). Based on the charge-domain coupling principle, a compact 10T1C SRAM CIM cell is designed. To accommodate the analog output characteristics, a low-offset comparator and an efficient input driver circuit are further developed. In the proposed architecture, three convolutional layers (Conv2~Conv4) of a five-layer BNN are mapped onto the CIM array to accelerate convolution operations in BNN inference. Meanwhile, to avoid frequent off-chip memory accesses during multi-layer convolution processing, a sliding-window-driven data scheduling mechanism is adopted to complete the inference process. Implemented in a 180 nm TSMC process, the architecture achieves an average power consumption of 38.67 μW and an average energy efficiency of 243 TOPS/W, demonstrating strong potential for microwatt-level edge vision inference applications.
For long-life products, the FPGA bitstream stored in NOR Flash may experience bit flips due to floating-gate charge leakage, which leads to FPGA configuration failure. To address this issue, this paper proposes a Flash refresh method based on FPGA multiboot. The Flash is refreshed during annual product maintenance to restore the floating-gate charge. The multiboot of the Kintex-7 series FPGA was investigated, and the configuration data composition was restructured to enhance the robustness of configuration. The optimized configuration data comprises one header file, two identical copies of the bitstream, and three identical sets of auxiliary file. When launching the Flash refresh, FPGA executes a sequence of steps including self-check, data refresh, and read-back verification to ensure the reliability of the process. The test results have verified that this refresh method is stable and reliable, exhibiting high practical engineering utility.
To address the complex challenges of modern new energy vehicles, such as low network transmission latency and high real-time data requirements, a vehicle gateway controller based on CAN FD (Controller Area Network Flexible Data-rate) was designed using Renesas automotive-grade microcontroller RH850/F1K. It features six bus channels, supports both classical CAN and CAN FD, and provides data storage. The bus transceiver employs the next-generation CAN transceiver TJA1462 to enhance signal transmission performance. The software design is based on the embedded operating system FreeRTOS, enabling multitasking and structured hierarchical functions. Additionally, a specialized driver was developed for the CAN peripheral’s unique transceiver method on the RH850/F1K microcontroller. Using a USB-to-CAN tool, the gateway’s data transmission and storage capabilities were tested. The results demonstrate that the designed gateway controller can operate smoothly even when the load rate approaches the bus usage limit, providing an efficient and reliable solution for vehicle gateway controllers.
This paper presents a bandwidth and resolution-configurable discrete-time Delta-Sigma modulator based on switched-capacitor circuits. To address the diverse requirements for measurement precision, signal bandwidth, and dynamic range in various industrial applications, the modulator features a reconfigurable loop filter architecture that can switch between third-order and fourth-order modes via an external control signal. Concurrently, the system enables the collaborative adjustment of signal bandwidth and resolution by adapting different oversampling ratios (OSRs). System modeling and simulations were conducted using MATLAB (OSR = 200). Regarding stability, the third-order mode demonstrates substantially relaxed conditions, yielding a Maximum Stable Amplitude (MSA) of -4.4 dBFS. This represents an optimization of 15.2 dB relative to the fourth-order mode (-19.6 dBFS), rendering it appropriate for large-amplitude signal processing. In terms of resolution, the fourth-order mode demonstrates superior noise-shaping capabilities, achieving a dynamic range (DR) of -154.4 dBFS, a 24.8 dB improvement over the third-order mode (-129.6 dBFS), enabling the precise resolution of weak signals. To verify the configurability of bandwidth and precision, performance metrics were tested under varying OSRs. Simulation data indicate that in the low-OSR region (OSR<20), the third-order modulator provides a superior Signal-to-Quantization-Noise Ratio (SQNR).
To address the challenges of stability assessment resulting from changes in the center of gravity after the renewal of ship equipment, as well as the problems of high cost, long time consumption and difficulty in popularization of traditional inclining tests on small and medium-sized fishing vessels, an automatic ship stability measurement system based on embedded technology is designed. The system employs an inertial measurement unit (IMU) as the core sensing module to realize high-precision measurement of ship roll attitude angle and rapid calculation of metacentric position through multi-source attitude data acquisition, embedded real-time processing and wireless transmission. Based on a master-slave architecture with the STM32F401 microcontroller as the core controller, the system integrates an accelerometer and an ultrasonic ranging module, and transmits data to a host computer via 2.4 GHz wireless communication, enabling multi-dimensional perception of the vessel’s dynamic response under slight inclinations. In the outdoor model ship test environment, the system significantly simplifies the measurement procedure through an automated process. Compared with the traditional manual calculation and observation, the single measurement time is greatly reduced. The average relative error of metacentric height measurement is less than 3%, which verifies the high efficiency of the system in data acquisition and algorithm solving. This system provides an efficient, cost-effective and field-operable solution for the stability safety assessment of fishing vessels after equipment renewal, meeting the demand for rapid on-site measurement in marine engineering.
Aiming at the technical bottlenecks of limited functionality, inadequate measurement precision and restricted data transmission methods inherent in conventional current data sampling modules, this study develops a high-precision current data acquisition module based on STM32 series microcontrollers. The module integrates a high-performance analog-to-digital (A/D) conversion chip and a network communication interface, thereby enabling high-precision sampling of 0~0.5 A DC current signals and real-time data transmission. Field test results indicate that the proposed current data acquisition module exhibits stable operation and high data accuracy with a measurement deviation of ≤0.078% after calibration and an electronic noise of ±0.18 μA. It can fully meet the application requirements of multi-point current monitoring in industrial workshops, and thus demonstrates strong potential for engineering application and practical implementation.
To address the predictability issue of interrupt latency in real-time operating systems (RTOS) undermulticore heterogeneous architectures, this paper proposes a layered interrupt latency modeling method and a comprehensive benchmark testing framework, using the domestic RK3588 chip and SylixOS real-time operating system as research subjects. Theoretical modeling is employed to analyze the impact of hardware architecture and operating system scheduling strategies on interrupt response time, and a testing scheme incorporating multiple scenarios such as single-core idle, mixed load, and full-core high pressure is designed. The proposed modeling-testing-optimization methodology provides a systematic reference for real-time evaluation and optimization of multicore heterogeneous platforms.
To address the low efficiency and high false positive rates of traditional SSI absolute encoder testing, this paper presents an FPGA-based automated defect detection system. The system adopts a dual-processor architecture, integrating an FPGA and an STM32 microcontroller. The FPGA performs SSI communication parsing, data acquisition, and real-time detection of anomalies such as skipping, looping, and dead codes, while the STM32 handles stepper motor control and user interaction. By integrating the incremental dynamic-threshold algorithm with high-speed buffering logic, the proposed system enables real-time analysis and accurate anomaly detection of encoder outputs. Experimental results demonstrate that the proposed system achieves high detection and recognition accuracy and is capable of effectively resisting interference in complex environments.The proposed system offers a cost-effective, high-performance solution for efficient and reliable encoder inspection and quality control in industrial applications.
To address the high cost and extended downtime associated with manual maintenance for aerospace sealed-cabin equipment, this paper proposes a reliable over-the-air (OTA) upgrade solution. The method adopts a dual-image backup mechanism with integrity verification and adaptive network protocols, enabling secure firmware updates of up to 16 MB and automatic rollback in the event of failure. Experimental results show a misdetection probability below 9.32×10-10, while approximately doubling the Flash lifespan, a 99.9% upgrade success rate, and 100% fault recovery. Compared to traditional manual methods, this approach reduces maintenance time from hours to about one minute and lowers costs by over 90%, effectively resolving key maintenance challenges.
