Neural ordinary differential equation (ODE) network inference in Von Neumann architectures faces problems like the "power wall" and "memory wall". Traditional in-memory computing architectures also suffer from excessive time and power consumption due to numerous digital-to-analog and analog-to-digital conversions. To address these issues, we propose a fully analog compute-in-memory architecture for Neural ODEs based on RRAM to achieve fully analog data flow in network inference. The simulation is completed on the Cadence Virtuoso platform, which includes RRAM device, array, and the peripheral circuits. The test is performed on a 40 nm RRAM test platform and differential input/output PCB, achieving functional verification of the entire system. Experiments and evaluations of the classification tasks of Neural ODEs are conducted with testing errors, ultimately proving the functionality and reliability of the architecture. This lays a solid foundation for subsequent hardware implementation and application deployment.
This study proposes a design method for a multi-channel DMA controller based on the AMBA AHB bus protocol. It puts forward a relatively complete design scheme for the multi-channel DMA controller, and provides detailed module designs. Through the multi-channel design, channel arbitration enables the two channels with the highest priority to alternately read and write, thereby preventing prolonged bus occupation by a single channel that could block other transfers. And resource consumption is reduced through time division multiplexing. Moreover, potential interactions with external devices are considered, improving transmission efficiency while reducing overall resource utilization.
Frequency standards play a vital role in modern science technology and industry. To address the issue of poor long-term stability in constant temperature crystal oscillator caused by factors such as crystal aging and temperature variations, this paper designs a constant temperature crystal oscillator frequency locking system based on a phase-locked loop (PLL) structure. The system utilizes the GPS signal received by the u-blox NEO-M8N module as the reference source, and employs STM32F103C8T6 as the control chip to lock the frequency of the constant temperature crystal oscillator OC5SC25 through the PLL structure. Using the extended Kalman filter and PID control algorithm, the long-term stability of the primary frequency standard and the short-term frequency accuracy of the secondary frequency standard are combined. The test results show that the system realizes the frequency lock of the 10MHz constant temperature crystal oscillator, enabling the frequency of the constant temperature crystal oscillator to operate at a higher stability and accuracy. Its average frequency accuracy reaches 3.28×10-12, which is nearly 4 orders of magnitude higher than the initial frequency accuracy. This effectively improves the limitations of the constant temperature crystal oscillator in long-term stability.
High Definition Multimedia Interface (HDMI) technology is widely used in daily life. Therefore, the functional verification of the HDMI-CEC (Consumer Electronics Control) interface has become increasingly important. This paper designs and implements a verification platform for the HDMI-CEC interface based on the Universal Verification Methodology (UVM). The platform is capable of generating constrained random test excitations through its modular design. The functional coverage and code coverage are used to evaluate the completeness of verification. In this study, the automated testing process and coverage-driven verification strategy provided by UVM are employed, resulting in a significant improvement in verification efficiency and accuracy compared to traditional methods. The core components of the verification platform are extended through UVM's standardized class library, ensuring the platform's reusability, scalability, and maintainability. The verification results show that the verification platform can effectively cover the various function points of the HDMI-CEC interface, so that the function coverage and code coverage are 100%, verify the validity and stability of the design. The research results provide an efficient and reliable solution for the verification of HDMI-CEC interface, highlighting its significant value in practical engineering applications.
To address the limitations of SoC platforms in supporting professional video transmission in airborne environments, this paper proposes an FPGA-assisted airborne video processing and transmission system based on the RK3588. Serving as the core processing unit, the RK3588 is responsible for real-time video stream acquisition, target detection, and image enhancement. The processed video is then transmitted to the FPGA module via the MIPI-DSI2 interface. Considering that the MIPI-DSI2 interface is not suitable for long-distance or high-interference transmission scenarios, the FPGA module adopts a triple-frame buffering mechanism and performs image format conversion and SDI encoding to generate video streams compliant with the SMPTE standard. This ensures reliable video transmission quality and system stability under complex airborne conditions. The experimental results demonstrate that the proposed system effectively meets the demands of high-performance video processing and transmission in airborne applications.
High-speed SerDes rates have progressed from 56 Gb/s to 112 Gb/s and beyond. Maintaining signal integrity at such ultra-high speeds while balancing power consumption, reliability, flexibility, and cost-effectiveness is a hot topic in current research. This paper reviews key technologies for 112 Gb/s SerDes from four perspectives: transmitter, receiver, clock structure, and low-power techniques, based on the current mainstream architecture of analog-to-digital conversion and digital signal processing. This exploration is provided as a reference for research related to high-speed SerDes technology.
For application scenarios requiring multi-channel high-speed acquisition and stable synchronization between channels, a multi-channel synchronous acquisition scheme based on Field-Programmable Gate Array (FPGA) is designed and implemented. This scheme adopts FPGA as the control and processing core, employs high-speed Analog-to-Digital Converters (ADC) to build sampling channels, and designs a stable clock and synchronization scheme, thus realizing a multi-channel synchronous acquisition system under high sampling rates. The feature of this solution is that it can monitor and adjust the synchronization status among multiple channels in real time, and it can be conveniently extended to synchronous acquisition among boards. The test results show that the data collected across all channels remains stably synchronized every time the system is powered on or off.
To meet the requirements of overcurrent protection for industrial equipment, a modular design-based electronic circuit solution is proposed, aiming to achieve precise current detection and rapid protection response. The modular design architecture integrates current sensing amplifier, hysteresis comparator and relay to function collaboratively. The current sensing amplifier is used to achieve signal acquisition with 0.1 mA level accuracy, the hysteresis comparator is used to set the protection threshold, and the solid-state relay is used to control the circuit's on-off. The experimental results show that when the current exceeds the set threshold, the circuit completes the disconnection action within 10 ms, and remains open even when the threshold current drops below the threshold, thereby avoiding false recovery. After multiple cycle tests, the protection action accuracy rate reaches 98.4%, effectively eliminating potential damage to the equipment caused by multiple overcurrents. This study provides an innovative solution for high-precision current protection in industrial applications.
To address the challenges of size constraints, energy efficiency, and complex background environments in real-time vehicle detection for micro unmanned aerial vehicles (UAVs), this paper proposes a low-cost solution based on Field-Programmable Gate Arrays (FPGA) that integrates a Position-Weighted Gradient Histogram (PWGH) with Support Vector Machines (SVM). The method extends the traditional 9-bin Histogram of Oriented Gradients (HOG) into a 9×2 composite histogram to enhance feature discrimination. Evaluated on the UAV_ROD dataset, the approach achieves an 8.4% improvement in accuracy. Implemented on the Zynq7020-mini platform, it processes at 50 frames per second with a power consumption of only 2.3 W. The experimental results validate the scheme's advantages in accuracy, processing speed, low power consumption, and miniaturization, demonstrating significant potential for practical engineering applications in UAV-based real-time vehicle detection.
This paper proposes a spatial array-based processor core design, eliminating the need for centralized register files. Through the design, computing units communicate data via an interconnect bus and perform computations directly through local memory. The processing results from local computing units are propagated to other units via a broadcast bus. This organization exhibits linear scalability, as the scale of computing units is not constrained by centralized components. It further incorporates flexible broadcast and reduction mechanisms that better align with algorithmic data communication patterns, facilitating efficient algorithm mapping and physical implementation. The processing element array implemented based on this design has high performance scalability, with a unit area performance of up to 1.4 TOPS/mm2@INT8, the performance to power ratio reaches 2.47 TOPS/W. This makes it well-suited for large-scale deployment as a high computing power processor processing core.
