With the rapid development of frontier fields such as aerospace, deep space exploration, and quantum computing, electronic systems are required to operate reliably under extreme temperature conditions, particularly at cryogenic temperatures. Silicon-Germanium Heterojunction Bipolar Transistor (SiGe HBT) have emerged as a promising candidate for wide-temperature-range analog/mixed-signal integrated circuits due to their high performance and compatibility with silicon-based processes. However, existing commercial compact models, such as HICUM and Mextram, exhibit insufficient accuracy at cryogenic temperatures, limiting their applicability. This paper presents an improved Mextram-based compact model for SiGe HBT operating from 80 K to 400 K. Key enhancements include temperature-dependent modeling of ideality factors and saturation currents in both the main current and base current models, as well as the incorporation of a heterojunction barrier effect model. A comprehensive characterization methodology and parameter extraction strategy for DC and RF behaviors across the wide temperature range are also proposed. Experimental validation shows that the proposed model exhibits excellent consistency with measured data, with an average relative error of less than 20% for the DC characteristics, demonstrating its accuracy and practicality for extreme-environment circuit design.
Temperature is a key variable that impacts the performance, reliability, and energy efficiency of modern integrated circuits. Leveraging the low cost and high integration of standard CMOS processes, CMOS temperature sensors have become widely deployed in conventional temperature ranges for consumer, automotive, power/battery-management, and SoC thermal-monitoring applications. Meanwhile, emerging cryogenic electronics,especially quantum computing,drives on-chip thermometry toward 77 K, 4 K, and even sub-kelvin regimes, where continuous sensing across room-to-cryogenic temperatures and calibration portability become major challenges. This paper provides a systematic review of CMOS temperature-sensing technologies spanning room temperature to cryogenic operation. We first summarize mainstream room-temperature implementations, including hybrid BJT/MOS PTAT/CTAT schemes, resistor-based sensors using various TCR elements, and time/frequency-domain readouts (e.g., ring-oscillator approaches), and compare their uncertainty, energy, area, and calibration cost. We then discuss how cryogenic device physics,such as BJT freeze-out, MOS threshold-voltage evolution, and the behavior of SiGe devices,affects transduction gain, linearity, and mismatch/noise. Finally, we survey representative Cryo-CMOS temperature sensors targeting 4 K and beyond, together with their linearization and calibration strategies, and highlight key trade-offs in temperature range, resolution, power, area, and scalability for multi-point thermal monitoring in both conventional SoCs and quantum-control ICs.
This paper presents a programmable computing-in-memory circuit based on a 4T GC-eDRAM cell, designed for cryogenic applications. First, a dual word-line readout structure is proposed to prevent data corruption in the memory cell. Second, leveraging the characteristic that computational data tends to be zero-biased, a zero-enhanced decoder/encoder circuit is proposed to further reduce read power consumption. Finally, a programmable near-memory computing circuit is implemented, capable of supporting both logic operations and arithmetic operations such as addition, subtraction, multiplication, and division. The design was fabricated and verified using a TSMC 65nm low power process. Experimental results demonstrate that the proposed circuit achieves a maximum speedup of 6× for convolution operations and 12.3× for lightweight data encryption. Within the temperature range of -40 ℃ to 85 ℃, the circuit exhibits superior read, write and computing energy efficiency compared to a 6T SRAM structure. It is worth noting that, as this circuit is based on a GC-eDRAM design, its performance is closely linked to leakage current and refresh frequency. As the temperature is lowered further into the liquid nitrogen range (77 K), the leakage current of MOS transistors is drastically reduced, enabling the refresh cycle to be significantly extended. This maximizes the circuit's energy efficiency ratio, endowing the designed circuit substantial advantages in low-temperature computing applications.
The stability of link establishment in the JESD204B interface protocol is a core prerequisite for ensuring the reliability of high-speed data communication, and it is vital for enhancing the performance of high-speed acquisition and transmission systems. To address the low link establishment success rates and inefficient fault localization of traditional JESD204B IP cores in harsh environments such as extreme high and low temperatures, this paper proposes an IP core optimization scheme to balance environmental adaptability and debuggability. This scheme adopts a hierarchical optimization strategy, introducing an XADC temperature acquisition module into the JESD204_phy core to dynamically configure high-speed interface parameters based on real-time temperature ranges, thereby enhancing the link's resistance to temperature drift. Additionally, a link establishment timeout response module is added to the JESD204_core core, which avoids link blockage caused by timeouts through error type classification statistics and ordered reset control, and provides a quantitative basis for fault localization. A verification system architecture of "ADC+FPGA" for data acquisition and transmission is constructed, and tests are conducted within a wide temperature range of -55 ℃ to 125 ℃. The test results show that the link establishment success rate under extreme temperature conditions is improved by approximately 8% compared to the traditional scheme. Furthermore, the optimized IP core effectively locates the cause of faults, verifying its high reliability and engineering practicality, which meets the high-speed data transmission requirements in harsh environments.
For the hot backup working mode of dual-channel redundant electronic controllers, a design scheme of a multi-functional channel management module based on CPLD is proposed to achieve efficient data exchange and synchronization between primary and backup channels. Serial Peripheral Interface (SPI) is used for communication and synchronization, with the management module serving as the SPI communication host to implement data broadcasting to both primary and backup channels and direct bridging between them, while also possessing the capability to monitor communication data. Based on simulation verification, the serial communication management functions normally, with the delay caused by timing logic in SPI bridging and broadcasting being 30 ns, indicating good system real-time performance. Tests on the SPI data transmission function of the designed dual-channel redundant electronic controller show that data integrity is good in both serial loopback and SPI data exchange tests, meeting the design requirements.
DPWM is the core of digital control switching power supply. To address the conflict between the high resolution of DPWM and the system operating frequency, this paper designs a high-resolution DPWM scheme based on FPGA. A 4 ns 14 bit low-resolution delay unit is implemented based on the traditional counter-comparator structure, and a 100 ps 7 bit high-resolution delay unit is achieved using a carry delay chain. The novel hybrid structure proposed in this paper can independently adjust the high-resolution delay of the rising and falling edges and has a real-time self-calibration unit to ensure the adjustment accuracy of the delay line and prevent the gradient adjustment from crossing the low-resolution period and causing offset stability issues. This architecture uses a cascaded carry delay chain design and global PWM drive via a BUFG, enabling automatic global routing and improving system portability. The experiment results demonstrate that the high-resolution delay units of this architecture are all below 100 ps, with an average delay of 67 ps, and it has high linearity and monotonicity.
As a key technology for improving the performance and integration density of integrated circuits, the layout design of Multi-Chip Module (MCM) packaging has a significant impact on system performance and cost. Traditional design methods relying on simulations and experiments are inefficient and difficult to achieve effective trade-offs in complex design spaces. This paper proposes a thermal performance and cost collaborative design strategy integrating automated simulation, surrogate models, and multi-objective optimization algorithms. First, Python secondary development was used to realize the full-process automation of numerical simulations, greatly improving simulation efficiency. Then, a high-precision surrogate model between chip spacing and maximum temperature was established, and fast prediction of thermal performance was achieved based on Support Vector Regression (SVR). On this basis, combined with the MCM cost model, the improved NSGA-II multi-objective algorithm was adopted to efficiently search for the Pareto optimal front. The research results show that the obtained Pareto front curve is superior to the original layout scheme, and the automated framework and intelligent algorithms significantly improve the efficiency of MCM collaborative design, providing a basis for the trade-off between thermal performance and cost.
With the continuous scaling down of transistor technology nodes, achieving timing closure in nanoscale integrated circuits faces severe challenges. Although traditional circuit simulation can evaluate the performance of cell netlists and layouts, its computationally intensive nature results in prohibitively high time costs. This paper proposes a delay-optimization-sensitive cell prediction model that integrates Graph Convolutional Networks (GCN) and Multilayer Perceptrons (MLP). The approach first dynamically adjusts transistor sizes in the netlist based on input signal states, then employs GCN to parse cell netlist structures and generate homogeneous graph representations of transistor connectivity relationships and process parameters. Finally, these topological features are fused with conventional timing characteristics and fed into an MLP to predict cell optimization potential, thereby identifying delay-optimization-sensitive cells. The experimental results demonstrate prediction accuracy rates of 83.2% for the top 10 delay-optimization-sensitive cells with the highest optimization potential and 75.3% for the top 5 such cells. Compared to SPICE simulation, the time required to identify delay-optimization-sensitive cells is reduced from hours to minutes, achieving approximately 600 times acceleration. This method can accurately identify critical optimization targets, provide layout designers with transistor-level optimization parameters, and significantly improve timing closure efficiency.
In order to automatically connect the microwave communication link between the calling party and the called party in the low orbit satellite communication network, we build a specialized microwave PBX to achieve this function, and the microwave switch array adapter is a key component of the equipment. The adapter modular is designed on the PXI bus. Its system controller accesses the local I/O adapter following the ISA bus specification through the PCI bus bridge, thereby realizing the on/off control and telemetry status detection operation of the microwave switches. The PCI bus bridge is implemented using low-cost PCI9052, while the local ISA bus logic signal generation and I/O adapter circuit are programmed using a domestically produced FPGA circuit. After the modular development is completed, the main functions and performance are tested in the laboratory, satisfying the performance targets.
This paper introduces the working principle of a voltage-controlled current source circuit, which is an improved version of the traditional Howland current source circuit. It employs a differential operational amplifier (op-amp) circuit structure to construct a voltage-to-current conversion circuit. By using an FPGA to control the DAC output to generate different voltages, the circuit achieves current output ranging from 4 mA to 24 mA. The paper analyzes the impact of factors such as the op-amp, DAC, and resistor network on current output accuracy, providing guidance for component selection and circuit design. A compensation method using linear fitting is proposed, effectively improving current output accuracy. The constant current source circuit built using the SGM8249 operational amplifier was tested under temperature conditions ranging from -30℃ to 70℃. Within the current output range of 4 mA to 24 mA, the maximum error did not exceed 0.03 mA, and the relative full-scale error was less than 0.15%, meeting the requirement of current output accuracy less than 0.3% in actual engineering applications.
For debug and verification of SoC, power source related problem is commonly encountered. The existence of inner resistor of power source, path of layout, and chip package, are the factor of output voltage fluctuation accompanied with load changes. In the design of SoC, some circuit and modules are designed for debug, beside design for test. OSC (oscilloscope) is typical measure tool for analog circuit test, which is widely used for observing voltage variation over time. LA (logic analyzer) is typical measure tool for digital circuit test, which is used for observing digital circuit timing, logic, and data on bus. When LA is observing debug port which output system status, result can be combined with the signal that observed from OSC, which would be helpful for positioning and solving problem. For example, in the system with low voltage and high current, power saving can be realized by lowering voltage efficiently. Minimal effective operating voltage is affected by power source fluctuation. Analog and digital test combination will be helpful for analyzing the reason of fluctuation, optimize power fluctuation and improve the system performance.
