As electronic packaging technology advances towards high-density and highly integrated configurations, FC-CCGA packages are increasingly adopted in aerospace and other high-reliability applications due to their superior electrical and thermal performance and I/O density. These packages must withstand vibrational loads during launch and thermal cycling during in-orbit operation, with their core interconnect components susceptible to stress accumulation leading to thermomechanical fatigue failure, directly threatening the reliability and lifespan of the package devices. This study, based on the Anand model, constructs a comprehensive electro-mechanical 3D model encompassing chip bumps, solder columns, epoxy resin, and PCB substrate, systematically investigating the vibration and thermal fatigue reliability of FC-CCGA solder joints and bumps. The analysis includes impact response spectrum assessments pre-electrical and post-electrical reinforcement, simulating the stress-strain response of critical solder joints and bumps under thermal cycling loads, and evaluating the plastic strain distribution and evolution over time. Additionally, the Coffin-Manson model is employed to predict the thermo-mechanical fatigue life of the solder joints and bumps. Temperature cycling tests on packaged devices were conducted, observing morphological changes in solder joints at varying cycle counts. The experimental results align with simulation predictions, providing a theoretical basis and methodological support for optimizing solder joint structures and assessing their lifespan for high-reliability applications.
To achieve independent controllability and enhance the communication reliability of the EtherCAT Slave Controller (ESC), this paper proposes an FPGA-based redundant communication interface. The design adopts a modular architecture with the innovative integration of hardware modules, including link redundancy processing, multi-path frame forwarding, EtherCAT frame parsing, and configurable timing compensation. It supports dual-link redundancy backup and enables real-time detection and isolation of erroneous frames. The system performs automatic frame forwarding and achieves microsecond-level latency through parallel hardware processing. FPGA test results demonstrate that the interface maintains stable communication during single-link failures while consuming minimal hardware resources. The proposed solution effectively improves the fault tolerance and real-time performance of ESC communications, laying a solid technical foundation for the independent development of high-reliability industrial communication chips.
The stringent application scenarios of CPLD devices demand high-reliability testing with rigorous standards. To address issues such as the complexity and low efficiency of testing CPLD devices via host computers, a method for generating CPLD configuration vectors based on a logic analyzer is proposed. Using a domestic CPLD as an example, this method employs a logic analyzer to capture the JTAG download configuration data in real time. Through protocol decoding and in-depth analysis of the decoded configuration data, configuration vectors are generated based on the SVF standard statement format. The configuration vectors conversion and online configuration testing verification using ATE were completed. The test results effectively demonstrate the correctness of the generated configuration vectors and the feasibility of the proposed method, providing significant guidance for the subsequent use of ATE in automated mass production testing of CPLD devices.
To address the demand for miniaturized, and low-power Synthetic Aperture Radar (SAR) systems on unmanned platforms, this study developed a high-speed imaging micro-system leveraging heterogeneous System-in-Package (SiP) technology. The system integrates an FPGA, a DSP, multiple DDR3 memory chips, and a LDO. Comprehensive electrical, thermal, and mechanical simulations validated the system’s signal integrity, thermal management, and structural robustness. Electrical simulations confirmed that the key signals of DDR3-1600MT/s and 5 GT/s SerDes meet design requirements in terms of insertion loss, return loss, and crosstalk. Thermal simulations verified that the junction temperature of the chips remains controllable with the application of a cold plate. Mechanical analysis demonstrated that the stress under thermal cycling and vibration shock conditions remains below the material limits. Imaging experiments showed close agreement between point-target responses, real-world data, and MATLAB simulations, with key metrics such as the Peak Side Lobe Ratio (PSLR) meeting performance targets. These results demonstrate the micro-system’s viability for enabling lightweight, high-performance SAR processing on unmanned platforms.
Aiming at the performance degradation of discrete cosine transform (DCT) in video coding when processing non-stationary residual signals, this paper proposes a frequency-domain transform optimization method based on reversible structural perturbation. Without modifying the kernel of the standard DCT transform, this method preprocesses the prediction residuals via a set of reversible row cyclic shift operations to adjust their spatial statistical distribution, making it closer to the optimal working region of DCT and thus improving transform coding efficiency. The algorithm dynamically calculates the offset according to the width and height of the coding unit (CU), and adaptively selects the optimal perturbation mode (including the non-perturbation mode) using a rate-distortion optimization mechanism. The mode indicator is signaled in the bitstream with extremely low overhead, and lossless reconstruction of the residuals is realized at the decoder through the corresponding inverse perturbation. Experimental results based on three full-HD test sequences in Class B of the JCT-VC standard show that the proposed method can achieve an average bitrate reduction of approximately 1.91% in overall tests with mixed CU sizes and prediction modes. The performance gain is especially significant in inter-prediction modes and large-size CUs. Specifically, a bitrate reduction of 2.80% is obtained for 4096-pixel CUs in the ParkScene sequence, and the algorithmic gain exhibits a U-shaped characteristic of "high at both ends and low in the middle" as the CU area increases. The proposed method effectively improves compression performance while maintaining computational complexity similar to that of the standard DCT, providing a new idea for hardware-friendly optimization of the transform module in video coding.
To address the problem of cross-scene object tracking, this paper proposes a scene transformation-based algorithm for stable object tracking. By integrating a feature enhancement module and an object refinement module into the Kernelized Correlation Filter (KCF) algorithm, the contour and detailed information of the target are highlighted. Meanwhile, the U-Net neural network is introduced to accurately detect scene boundaries, and a dynamic update and target reacquisition strategy is incorporated into the decision-making framework to ensure stable object tracking. Given that the proposed algorithm fails to meet real-time performance requirements due to increased computational complexity, the Atlas 300I edge computing module is adopted for algorithm acceleration. This approach effectively balances the trade-off between algorithm complexity and tracking performance, improving tracking accuracy while satisfying the real-time constraints of practical engineering applications. The experimental results demonstrate that the proposed algorithm can effectively resolve the issue of tracking drift in cross-scene object tracking scenarios, providing valuable insights for future research in this field.
In response to the pressing industrial demand for high-efficiency and low-power embedded 3D measurement systems, this paper presents an FPGA-based 3D measurement system by employing a half-period fringe binary encoding algorithmic architecture. The system first captures structured light images via a camera control module, followed by image buffering and filtering preprocessing. Leveraging the parallel processing capability of FPGA, hardware acceleration is implemented for key algorithmic modules including wrapped phase calculation, phase unwrapping, and 3D point cloud reconstruction. Finally, the reconstructed results are transmitted to the host computer for visualization through a Gigabit Ethernet module, establishing a complete embedded 3D measurement pipeline. The experimental results demonstrate that the proposed system achieves a single 3D reconstruction time of 4 ms for images with a resolution of 720×540, with a system power consumption of 1.687 W and a fitting error of 0.053 2 mm in standard sphere measurements. These findings indicate that the system exhibits robust performance and practical utility while maintaining low power consumption, offering a viable solution for the implementation of embedded 3D measurement systems.
To address the data stream conversion problem between serial input and parallel output of four LCoS zones in 8K LCoS drivers for high-definition multimedia interfaces, and to meet the high-performance driving requirements of ultra-high-definition displays, this paper studies a frame buffer module based on DDR SDRAM. This paper summarizes three main innovations: First, for the 8K four-partition LCoS drive scenario, an AXI bus and FDMA IP core cooperative DDR control architecture is built. Flexible read/write partitioning of DDR memory enables independent parallel read/write for four regions, solving the data flow conversion problem between serial HDMI input and parallel LCoS output. Second, an image flip implementation scheme based on address mapping is proposed. Through flexible address control, vertical flip is achieved without additional logic modules, simplifying the design. Third, an asynchronous FIFO and synchronous signal module design solves the multi-clock-domain data stable transmission problem, with timing deviation ≤ 1 clock cycle, stably caching data with a resolution of 7 680×4 320 and support ≥ 3 frame pre-stores, achieving stable caching and efficient distribution of 8K resolution data. These innovations collectively ensure the stability and efficiency of 8K high-resolution data transmission and provide a reusable technical framework for frame buffer design in high-resolution multi-partition display drivers.
Against the dual backdrop of the accelerated advancement of domestic independent innovation and the explosive growth in demand for AI computing power, the localization of core underlying disk control technologies in storage systems remains inadequate. To address this issue, this paper designs and implements a SATA-standard NAS storage system based on the domestic software and hardware ecosystem. Its core hardware architecture adopts the Fudan Microelectronics FPGA and the Loongson 3A3500 processor, with the software layer built on the Kylin Linux operating system. The FPGA realizes the bridge conversion between the PCIe and SATA protocols, encompassing core functions such as high-speed PCIe data interaction, HBA controller logic, and SATA protocol processing. On this basis, combined with RAID redundant storage technology, a NAS storage management system integrating volume group management and multi-protocol file sharing is further designed and implemented. This work provides a feasible technical approach and practical solution for the localization of storage systems.
To address signal attenuation and reduced sensitivity in traditional ultrasonic anemometers under adverse conditions, such as precipitation, high-velocity winds, and dust, an ultrasonic anemometer featuring adaptive signal gain adjustment has been developed. The hardware architecture integrates driving and receiving stages, a programmable gain amplification and adjustment circuit, a filtering circuit, an analog-to-digital (AD) acquisition, and a central MCU. The system leverages a robust software suite combining time-difference, ringing, and cross-correlation methods, alongside a binary-search-based adaptive adjustment algorithm to calculate wind speed and direction. The experimental validation demonstrates that the anemometer maintains high precision and stability across challenging environmental conditions. It achieves an error of ±0.5 m/s within the 0~15 m/s range, while maintaining an error margin of within ±3% for speeds between 15~40 m/s. Across the full 0~40 m/s spectrum, the absolute wind direction error remains consistently below 3°.
Tailored for portable mass spectrometer, a miniaturized ion trap radio frequency power supply has been designed, mainly consisting of amplitude control circuit, frequency modulation circuit, power amplifying circuit, feedback circuit and resonant coil. The system delivers a peak-to-peak output voltage of 3.5 kV under the resonant frequency of 1 MHz. Using the RF power supply, the mass spectrometer's mass range is 15~620 amu with a resolution of 0.7 amu and exceptional long-term mass stability of better than 0.2 amu. Characterized by its compact architecture and high output stability, this RF power supply offers significant utility and practical value for the next generation of portable mass spectrometers.
