In industrial control algorithms, the calculation of mathematical functions typically requires a large number of clock cycles, affecting the performance of the algorithms. This paper conducts an in-depth analysis and comparison of related methods for calculating floating mathematical functions, and designs a piecewise table lookup polynomial fitting method based on the Remez algorithm. This method is suitable for hardware circuit implementation to calculate mathematical functions. At the same time, the corresponding hardware circuits are implemented in the form of RISC-V custom instructions, closely coupled with the RISC-V processor core. The experimental results show that compared with no custom extension instructions, the processor's delay in calculating mathematical functions is reduced by 93.62%. Compared with the method of calculating mathematical functions using the CORDIC instruction set, the calculation delay is reduced by 79.83%. This achievement provides new ideas and solutions for RISC-V architecture embedded microprocessors with low-cost, high real-time requirements.
In recent years, Silicon-Germanium Heterojunction Bipolar Transistors (SiGe HBTs) have not only achieved significant advancements in high-frequency performance but also demonstrated unique advantages in applications involving high-temperature electronic devices. This paper reviews the development of SiGe HBTs and explores their potential applications in high-temperature environments ranging from 100 to 300 °C. By now, the most advanced SiGe HBT have shown a transit frequency of 500 GHz and a maximum oscillation frequency of 700 GHz, highlighting their exceptional performance under high-frequency condition. Furthermore, SiGe HBTs have been integrated with 22 nm fully depleted silicon-on-insulator (FD-SOI) technology, forming the most scaled Bipolar Complementary Metal-Oxide-Semiconductor (BiCMOS) processes. This integration supports extremely high operating frequencies while enabling the cost-effective monolithic integration of advanced digital circuits with high-frequency transceivers. It paves the way for applications in millimeter-wave and terahertz bands such as automotive radar, satellite communications, and security imaging. A particular note is the superior performance of SiGe HBTs at high temperatures, characterized by low leakage current, high current gain, and cost-effectiveness. These attributes make SiGe HBTs an ideal choice for high-temperature electronic applications, showcasing substantial potential for reliable operation in extreme environments.
This paper presents a system-level memory protection unit based on bus matrix. The unit supports supervisor and user modes. It can not only be flexibly configured according to the number of bus matrix masters, but also monitor all masters’ activities in the system in real time, effectively preventing unauthorized masters from accessing specific memory areas. It addresses the functional safety problem of task interference caused by a single master-based memory access protection mechanism. In addition, the design supports the implementation of different protection strategies for the same memory region. This capability can protect the private data and shared data of each core, and solves the data consistency problem in multi-core system architecture with minimum hardware cost.
To address the issue of caches being unable to predict nonlocal program execution and prepare for critical tasks, this paper proposes a high-security, level-1 configurable instruction cache design. The design achieves flexible Cache/SRAM configurability through internal control registers. It ensures data access security for users at various levels through two granularity storage protection mechanisms: page-level and cache line-level. Rapid interaction with external storage data is achieved through direct memory access (DMA) to SRAM. A Universal Verification Methodology (UVM) verification platform is established to conduct module-level verification of the configurable instruction cache and collect coverage data. Different library functions are invoked to perform system-level verification and compare the hit rates of the cache under different L1P size configurations. A 40 nm low-threshold library is utilized to conduct post-simulation verification of latency and power consumption. The results demonstrate that the designed cache can safely and swiftly switch between five L1P configurations of 32 KB, 16 KB, 8 KB, 4 KB, and 0 KB during program execution, with a maximum path delay of 1.47 ns and a total power consumption of 309.577 mW, meeting the stable operation requirements of a 600 MHz high-performance DSP.
This article first introduces three main requirements of a phase-locked loop (PLL) for Frequency Modulated Continuous Wave (FMCW) radar systems: frequency modulation bandwidth, frequency modulation slope, and linearity. Then, based on highly cited and influential articles from the past decade, it analyzes the advantages and application challenges of digital phase-locked loops (DPLL) in FMCW systems and briefly outlines the existing methods to overcome these challenges. The development trends of phase-locked loops in relation to the three main requirements are summarized, and a new figure of merit definition is proposed to evaluate the performance of PLLs for FMCW systems. Finally, it is pointed out that digital phase-locked loops are a key research direction for developing high-performance FMCW systems in the future.
With the rapid increase of data volume in today's era, higher requirements are put forward for data transmission technology, especially in terms of transmission speed, stability and reliability. Traditional single channel LVDS data transmission system generally achieve transmission rates of only a few hundred Mb/s when transmitting over long distances, which is insufficient for high-speed data transmission needs. To address this challenge, this paper proposes a comprehensive optimization scheme. In terms of hardware, two groups of four channel LVDS chips are used as the high-speed data interface, enabling eight channel LVDS transmission and thereby improving the data transmission rate. However, as the rate increases, the probability of error code generation due to crosstalk and electromagnetic interference also increases. Therefore, it is necessary to cooperate with the anti-interference ability and long-distance transmission ability of dedicated LVDS data driver and cable equalizer system. In addition, RS encoding and decoding technology is introduced into the software logic to achieve error correction within a certain range. With automatic retransmission technology and CRC verification, the reliability of data transmission is improved. After extensive tests, the proposed design can finally achieve 4 000 Mb/s zero error transmission under 80 m twisted pair shielded cable.
The Least Mean Square algorithm, as a typical adaptive filtering algorithm, has found extensive application in the field of noise suppression. Its implementation is mainly based on general-purpose processors, yet this method suffers from low computational efficiency and performance. The RISC-V architecture, with the advantages of open-source, streamlining, and scalability, is suitable for the implementation of dedicated processors. In this paper, a RISC-V based specialized processor is designed for the LMS algorithm. The customized instruction set F extension is used to process floating point numbers, and MAC instructions are added to the coprocessor to complete the acceleration of the LMS algorithm. The experiment results show that the processor can realize effective noise cancellation, when the input signal-to-noise ratio is 5 dB, the signal-to-noise ratio after noise cancellation is 17.5 dB. When the system uses FPU to execute the LMS algorithm, the number of instruction execution is 220 354, and the execution cycle is 586 221. When this design scheme is used, operating in FPU+MAC mode, the number of instruction execution is 31 621, and the execution cycle is 89 412, demonstrating a remarkable improvement in efficiency.
This article reviews the development of CCD image sensor technology. Based on the high reliability application requirements of CCD image sensors, it analyzed the product characteristics of CCD, categorizes the main failure modes, and conducted in-depth research on the failure mechanism of CCD due to electrostatic damage and irradiation. Furthermore, typical experimental verification work has been carried out, and failure variation curves under different irradiation conditions are presented. This study provides both theoretical foundations and experimental data for the high-reliability evaluation and failure analysis of CCD, thereby offering technical guidance for the high-reliability application of CCD products.
As process nodes continue to shrink and device structures become increasingly complex with the three-dimensional designs of the device, the reliability of the device is becoming a critical concern in both academia and industry. In this paper, an in-depth study of the reliability of FinFET (Fin Field-Effect Transistor) devices has been carried out, and ageing experiments have been designed and conducted under the conditions of different numbers of fins (Nfin), drain stress voltages (Vdstress), gate stress voltages (Vgstress) and temperatures. Analysis of the test data indicates that the ageing phenomenon of FinFET devices increases with increasing Nfin, Vdstress, Vgstress and temperature. Based on these experimental results, a reliability aging model is developed with parameter optimisation employed to achieve an effective fit to the degradation of threshold voltage (Vth_lin) and saturation current (Idsat). The proposed model shows excellent simulation accuracy under different conditions, maintaining an average simulation error of less than 5 mV for the threshold voltage and within 1% for saturation current.
This paper discusses a high-precision geomagnetic navigation algorithm based on interpolation matching and completes the hardware design and implementation of the algorithm. The geomagnetic navigation module relies on the spatial distribution characteristics of the geomagnetic field for positioning, but traditional algorithms are susceptible to noise and errors in complex environments, leading to insufficient positioning accuracy. To address this, the paper combines an interpolation matching algorithm to construct a refined geomagnetic intensity distribution model, enabling efficient processing and precise matching of geomagnetic field information. Additionally, a low-power, high-performance hardware architecture is designed to facilitate rapid execution of the algorithm. This design significantly improves the speed and energy efficiency of positioning calculations while maintaining high positioning accuracy in complex environments. It can be widely applied in modern navigation devices, providing an efficient geomagnetic navigation solution.
