Short-wave infrared(SWIR) imaging technology, operating in the 1 ~2.5 μm electromagnetic spectrum, does not rely on object thermal radiation, is less affected by ambient illumination, fills the gap in full-band imaging, and holds significant value across multiple fields. This design develops an uncooled SWIR camera core system based on the ZYNQ platform and a domestic InGaAs focal plane array(FPA) detector to realize image acquisition, preprocessing, and transmission:hardware encompasses a main control board, driver board, TEC temperature control, power supply, and peripheral circuits, with output channels established via Camera Link and Ethernet, while software achieves PL-PS data interaction, completes link synchronization and data reception based on the JESD204B protocol, and optimizes image quality through an improved preprocessing algorithm. The system achieves stable output of 640×512 resolution at 30 f/s, boasting light weight, low power consumption, and low cost, which fully meets practical application requirements.
Facing the processing performance bottleneck of current satellite communication terminals in high-throughput IP service scenarios, this paper proposes a high-speed IP service transmission method based on a CPU+FPGA SoC architecture. The core of this method lies in the separation and cooperation of the control plane and the data plane. The functions required for high-speed data forwarding, such as IP access, route addressing, and link frame assembly/disassembly, are offloaded to the FPGA to form a high-performance data plane, control plane logic such as route maintenance and protocol interaction is handled by the CPU. Through key technologies of event-driven synchronization and hardware-level QoS scheduling, collaborative design challenges, including entry synchronization and low-latency signaling guarantee, are overcome. This achieves a significant performance leap on existing hardware, providing an effective solution for the smooth performance upgrade of large-scale in-network satellite terminals and the design of compact, low-power terminals.
The reliance on commercial EDA tools and the complexity of environment construction in traditional processor verification workflows often hinder agile development. To overcome these bottlenecks, this paper presents an agile, core-level verification methodology for RISC-V processors driven entirely by an open-source toolchain. By leveraging Verilator as the simulation engine and the Python-based Cocotb framework's coroutine mechanism, the proposed approach achieves both high-level abstraction of test stimuli and precise cycle-level driving. Furthermore, a lightweight test architecture is designed to accelerate the feedback loop. Case studies on the open-source RISC-V Ibex core demonstrate that, compared to the traditional Universal Verification Methodology(UVM), this scheme reduces code size by approximately 85% and compresses the iteration cycle of a single test case from hours to minutes-all while ensuring the effective verification of critical paths such as instruction execution and exception response. This solution significantly enhances early-stage design efficiency and offers a cost-effective alternative for educational experiments and prototype development.
To address the challenges of heavy maintenance tasks, difficult physical layer fault localization, and high communication latency associated with traditional "FPGA+ARM" dual-chip architectures in current MVB(Multifunctional Vehicle Bus) networks, this paper designs an MVB bus waveform acquisition and fault diagnosis system based on the ZYNQ heterogeneous SoC platform. First, leveraging the on-chip high-bandwidth interconnection characteristics of the Programmable Logic(PL) and Processing System(PS) in the ZYNQ architecture, a hardware-software co-design acquisition architecture is constructed, resolving the timing bottleneck of cross-chip transmission. Second, for common short-circuit, open-circuit, and impedance mismatch faults in the MVB physical link, a diagnosis method combining key time-domain feature extraction and an expert rule base is proposed. Decision thresholds are set based on the IEC 61375 standard and statistical criteria, replacing traditional single-threshold judgment. Finally, a semi-physical simulation experimental platform was built for system verification. Test results show that the system can accurately reconstruct high-speed MVB signal waveforms; in a laboratory environment, the end-to-end delay from acquisition to diagnosis is controlled at the millisecond level, and typical physical layer faults can be accurately diagnosed. This design achieves deep on-chip coupling of data acquisition and intelligent processing, providing a highly integrated engineering solution for train network status monitoring.
This work presents the design and implementation of a distributed gallium arsenide power amplifier with integrated temperature and power sensing for high-power ultra-wideband applications, based on a 0.15 μm-GaAs pHEMT process. The proposed amplifier consists of a distributed power amplifier, a temperature sensing unit, and a differential power detection unit. The distributed power amplifier adopts a cascode architecture, which significantly enhances the output power. The proposed temperature sensing unit employs a multi-point array-based temperature measurement scheme, in which different temperature sensing nodes can be selected through an external encoder. The differential power detection unit outputs detection voltages through the Vdet and Vref pins, effectively suppressing the influence of temperature variations on power detection accuracy. Simulation results indicate that, under the operating condition of Vgs=-0.3 V, the DPA achieves an operating bandwidth from DC to 28 GHz, with the output power increased to 30 dBm, a power-added efficiency of 15%, and a gain flatness better than ±1 dB. Small-signal simulation results demonstrate that, over the operating bandwidth, both the input return loss and output return loss are better than-10 dB. The overall chip layout area is 3.8 mm×1.5 mm.
The selection of aerospace components is a critical link in space missions. Traditional selection methods are plagued by issues such as low efficiency and high reliance on professional expertise. This paper designs and implements an intelligent selection and recommendation system for aerospace components based on large language models(LLMs) and retrieval-augmented generation(RAG) technology. Adopting an agent-based architecture, the system achieves end-to-end intelligent processing, converting users' natural language requirements into component recommendation schemes seamlessly. A professional knowledge base is constructed, encompassing 468 aerospace-grade components and 60 system-level bills of materials(BOMs). A multi-strategy cascaded retrieval mechanism integrating exact matching and semantic understanding is designed, and a hallucination prevention and control mechanism is developed to meet aerospace safety requirements. The system is capable of handling application scenarios including single component recommendation and system-level scheme generation. In an evaluation experiment involving 65 test cases, the system achieves a macro-average F1-score of 0.829, representing a 10.4% improvement over manual keyword retrieval and a 69.5% improvement compared to pure LLM methods, thus verifying the system's effectiveness. The intelligent selection and recommendation system for aerospace components proposed in this paper can effectively support the intelligent selection of aerospace components.
This paper presents the design and implementation of a highly efficient and stable electromagnetic wave energy harvesting circuit targeting ultra-high-frequency(UHF) RFID applications. The system consists of a rectifier, a reference circuit, and a voltage regulator, collectively providing a reliable power supply for other chip modules. Key achievements include a differential rectifier achieving 67% power conversion efficiency(PCE) with 1.84 V output at 11 dBm input power. An ultra-low-power CMOS reference circuit with temperature coefficients of 34.9 ppm/℃(voltage) and 18.4 ppm/℃(current), and a power supply rejection ratio(PSRR) better than-93 dB at 100 Hz. An LDO-based voltage regulator exhibiting a load regulation of 41.28 mV/mA under varying load conditions. Additionally, clock, reset, demodulation, and modulation circuits are integrated. The circuit is implemented in a 180 nm CMOS process, occupying a layout area of 341 μm × 346 μm. Post-layout simulations indicate a total power consumption of 6 μW. Silicon measurements confirm that all performance metrics meet the requirements for high conversion efficiency and power supply stability in UHF RFID chips.
The Host Port Interface(HPI) of a self-developed DSP enables high-volume host-DSP data exchange by allowing direct host access to DSP memory through a parallel bus. The limitations of the HPI interface are addressed in this paper in terms of bandwidth, portability, and compatibility with the Enhanced Direct Memory Access(EDMA) interconnection protocol, and a complete 16-bit HPI interface based on the Advanced High-performance Bus(AHB) protocol is proposed and designed. The design adopts a modular approach and is implemented in Verilog, including the register configuration module, AHB slave interface module, read cache and control module, host port interface module, and write cache and control module. Functional verification and logic synthesis of the host̓s read and write access to the HPI were conducted. The synthesis report indicates that at a 40 nm process and 200 MHz operating frequency, the overall area of the HPI interface based on the AHB bus is 10 344 μm2, with a bandwidth of 66 MB/s and a dynamic power consumption of only 0.386 mW. The verification results show that the HPI interface, while achieving data transmission, realizes burst data transmission between the AHB protocol and EDMA, providing a high-bandwidth, easy-to-implement host parallel communication interface with stronger portability and broad applicability.
FPGAs are extensively employed as interface boards in embedded systems. The software operating on these chips primarily interacts with peripheral devices. A significant challenge in verifying such FPGA software lies in developing configurable simulation models, supporting both normal and abnormal operations, based on peripheral chip specifications. Currently, these simulation models are predominantly implemented as static constructs using System Verilog/Verilog-HDL/VHDL language features. These simulation models, akin to RTL models, exhibit a structured nature. This implies that their configuration is static without supporting dynamic instantiation or teardown during the simulation. Therefore, this type of simulation model is suitable for verification scenarios in which the chip's operating mode remains unchanged during runtime. For verification scenarios where the operating mode needs to switch during runtime, using a static simulation model to simulate such scenarios requires the development of a communication interface with the verification platform. Furthermore, since UVM verification platforms cannot dynamically instantiate such static simulation models, embedding them into a UVM environment prevents utilizing UVM's powerful class library ecosystem. To address the issues mentioned above, this paper employs the UVM standard class library, which leverages the object-oriented features of System Verilog, to construct a simulation model of peripheral chips. This simulation model is then embedded into the UVM verification platform. Experimental results demonstrate that the verification platform can dynamically configure the operating modes of the simulation model during runtime. In other words, the model is capable of simulating scenarios that involve switching between multiple operating modes of peripheral chips, thereby enriching the verification scenarios for FPGA software. The chip simulation model proposed in this paper, based on the UVM standard class library and integrated with the UVM verification platform, reduces to some extent the simulation complexity of peripheral chip multi-mode switching scenarios and alleviates the development and maintenance difficulties associated with simulation models for peripherals featuring multiple operating modes. This approach provides a new and feasible solution for developing simulation models in the verification of FPGA software related to interface timing control.
To study the immunity of power chips to conducted electromagnetic interference, an electromagnetic pulse generator is designed based on the IEC 61000-4 series standards. First, mathematical models and their equivalent circuit models are proposed for the electromagnetic interference pulses in the existing standards, and the conversion relationship between the two is given. Then, based on the equivalent circuit model and relay switch, an electromagnetic interference generation module is fabricated and equipped with a main control module, high-voltage DC module, and display module to form an integrated testing device. Finally, the designed electromagnetic pulse generator is validated in the time domain. The results indicate that the output waveform of the designed electromagnetic pulse generator has high accuracy and can provide various pulse characteristic test waveforms for power chips.
Facing the new era̓s cybersecurity situation, China has timely proposed an active immune protection system based on trusted computing 3.0. Combined with the national standard specifications of the Trusted Platform Control Module(TPCM) in China, a TPCM module solution based on a secure SSD and its implementation method are proposed. Through the built-in SM2, SM3, SM4, random number generator module, and OTP controller module of the security control chip, the power-on self-test, secure boot, data encryption and decryption, and key management functions of the security control chip are realized. Based on the secure SSD, an authentication software is designed to achieve the trusted boot measurement and response of the physical environment such as the computer motherboard, BIOS, peripherals, and IP address. Compared with the existing TPCM cards, the proposed solution brings the credibility measurement forward to the secure and trusted boot of the SSD, which has the advantages of high security, good compatibility, strong scalability, convenient deployment, and low cost.
Addressing the issues of short endurance and frequent maintenance of untethered photovoltaic panel cleaning robots in scenarios without grid power, this paper designs a low-power embedded system based on hardware and software collaborative optimization. The system uses the ultra-low-power microcontroller STM32L496 as the core, constructs a hierarchical power management circuit including an efficient DC-DC converter and a low quiescent current LDO, designs software-controllable independent power switches for peripheral modules such as communication and sensors, and optimizes low power consumption for the adaptive working conditions of the strong current servo system. A timing wake-up mechanism based on the Real-Time Clock(RTC) and a dynamic power management strategy are implemented on FreeRTOS, enabling the system to enter a deep sleep state with microampere-level power consumption during non-operating periods. Theoretical modeling and analysis show that compared to the scheme without low-power optimization, the average power consumption of this system under typical working cycles is reduced by approximately 82.2%. The theoretical endurance of the robot equipped with a 10000mAh lithium battery is extended from 7.2 days to 40.5 days, significantly improving its continuous operation capability and operational and maintenance economy.
