Digital interface design for analog SRAM memory computing integrated chip

KONG Helin; WEI Zhixing; CHEN Tingran; PAN Biao

doi:10.20193/j.ices2097-4191.2025.0030

PDF(10075 KB)

Integrated Circuits and Embedded Systems ›› 2025, Vol. 25 ›› Issue (7) : 1-8. DOI: 10.20193/j.ices2097-4191.2025.0030

Cover Article

Digital interface design for analog SRAM memory computing integrated chip

Author information +

History +

Abstract

Neural network models demand high processor performance and energy efficiency. The memory-computing integrated architecture is an energy-efficient solution. This paper introduces a digital interface simulation scheme to address simulation verification challenges in analog memory-computing integrated designs and improve simulation efficiency in large-scale computing scenarios. The scheme analyzes SRAM-based memory-computing integration and combines the SPICE model with a digital control circuit. This enables the use of digital methods for simulation and verification, potentially boosting development efficiency. An evaluation system comparing the digital interface simulation with traditional analog circuit simulation reveals that the new solution increases simulation speed by more than 2 times and configuration efficiency by more than 1 000 times. This research is supported by the key research and development program of the ministry of science and technology (2021YFB3601300), and this research has been validated with tape-out at the 180 nm process node, demonstrating the efficiency advantages of the digital interface simulation scheme for memory-computing integrated design in large-scale computing.

Key words

ASIC / computing in memory / mixed signal simulation / analog SRAM

Cite this article

EndNote

Ris (Procite)

Bibtex

Download Citations

KONG Helin , WEI Zhixing , CHEN Tingran , et al. Digital interface design for analog SRAM memory computing integrated chip[J]. Integrated Circuits and Embedded Systems. 2025, 25(7): 1-8 https://doi.org/10.20193/j.ices2097-4191.2025.0030

References

List( Publishing order | Descend order by publishing year | Descend order by cited within ) Chart analysis

[1]	M AZIDAN, J P STRACHAN, W D LU. The future of electronics based on memristive systems[J]. Nature electronics, 2018, 1(1):22-29. Cited in this article [1]

[2]	XUE C, CHANG M. Challenges in Circuit Designs of Nonvolatile-memory based computing-in-memory for AI Edge Devices[C]// 2019 International SoC Design Conference (ISOCC), 2019:164-165. Cited in this article [1]

[3]	C JJHANG, C X XUE, J M HUNG, et al. Challenges and Trends of SRAM-Based Computing-In-Memory for AI Edge Devices[J]. IEEE Transactions on Circuits and Systems I:Regular Papers, 2021, 68(5):1773-1786. Cited in this article [2]

[4]	DONG Q, SINANGIL M E, ERBAGCI B. A 351TOPS/W and 372.4GOPS compute-in-memory SRAM macro in 7nm FinFET CMOS for machine-learning applications[C]// 2020 IEEE International Solid-State Circuits Conference, 2020:242-247. Cited in this article [1]

[5]	WANG J C, WANG X W, ECKERT C, et al. A compute SRAM with bit-serial integer/floating-point operations for programmable in-memory vector acceleration[C]// 2019 IEEE International Solid-State Circuits Conference, 2019:224-226. Cited in this article [1]

[6]	WANG J, WANG X, ECKERT C, et al. A 28-nm Compute SRAM With Bit-Serial Logic/Arithmetic Operations for Programmable In-Memory Vector Computing[J]. IEEE Journal of Solid-State Circuits, 2020(1).DOI:10.1109/jssc.2019.2939682. Cited in this article [1]

[7]	Y D CHIH. 16.4 An 89TOPS/W and 16.3TOPS/mm² All-Digital SRAM-Based Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning Edge Applications[C]// 2021 IEEE International Solid-State Circuits Conference (ISSCC), 2021:252-254. Cited in this article [1]

[8]	ZHANG J, WANG Z, VERMA N. In-Memory Computation of a Machine-Learning Classifier in a Standard 6T SRAM Array[J]. IEEE Journal of Solid-State Circuits, 2017, 52(4):915-924. Cited in this article [1]

[9]	A AGRAWAL, A JAISWAL, C LEE, et al. X-SRAM: Enabling In-Memory Boolean Computations in CMOS Static Random Access Memories[J]. IEEE Transactions on Circuits and Systems I:Regular Papers, 2018, 65(12):4219-4232. Cited in this article [1]

[10]	Z JIANG, S YIN, J S SEO, et al. C3SRAM:In-Memory-Computing SRAM Macro Based on Capacitive-Coupling Computing[J]. IEEE Solid-State Circuits Letters, 2019, 2(9):131-134. Cited in this article [1]

[11]	JIANG H W, PENG X C, HUANG S S, et al. CIMAT: a transpose SRAM-based compute-in-memory architecture for deep neural network on-chip training[C]// 2019 Proceedings of the International Symposium on Memory Systems, 2019:490-496. Cited in this article [1]

[12]	YU S, JIANG H, HUANG S, et al. Compute-in-Memory Chips for Deep Learning: Recent Trends and Prospects[J]. IEEE Circuits and Systems Magazine, 2021, 21(3):31-56. Cited in this article [1]

[13]	M E SINANGIL. A 7nm Compute-in-Memory SRAM Macro Supporting Multi-Bit Input, Weight and Output and Achieving 351 TOPS/W and 372.4 GOPS[J]. IEEE Journal of Solid-State Circuits, 2021, 56(1):188-198. Cited in this article [1]