Applications and major challenges of glass core substrate for chiplet integration

CHEN Changhao, XU Shimeng, LIN Pengrong

Integrated Circuits and Embedded Systems ›› 2025, Vol. 25 ›› Issue (9) : 1-13.

PDF(33463 KB)
PDF(33463 KB)
Integrated Circuits and Embedded Systems ›› 2025, Vol. 25 ›› Issue (9) : 1-13. DOI: 10.20193/j.ices2097-4191.2025.0025
Cover Article

Applications and major challenges of glass core substrate for chiplet integration

Author information +
History +

Abstract

The growing demand for massive data processing such as artificial intelligence has greatly promoted the development of chiplet integration technology, which further imposes technical requirements on FC-BGA substrates, including large size, low warpage, electrical performance and high reliability. The late-model glass core substrate has attracted extensive attention owing to its intrinsic low dielectric coefficient, high thermal stability and chemical inertness. However, current glass core substrate technology remains in the initial stage of mass production, lacking comprehensive, reliable and standardized methods of producation, application and testing. This article overviews the history, characteristics, and present challenges of glass core substrate. It also provides a summary and prospect on the future applications of glass core substrate in chiplet integration.

Key words

chiplet integration / glass core substrate / through glass vias

Cite this article

Download Citations
CHEN Changhao , XU Shimeng , LIN Pengrong. Applications and major challenges of glass core substrate for chiplet integration[J]. Integrated Circuits and Embedded Systems. 2025, 25(9): 1-13 https://doi.org/10.20193/j.ices2097-4191.2025.0025

References

[1]
CHEN W, BOTTOMS W R. Heterogeneous integration Roadmap[C]// 2017 International Conference on Electronics Packaging (ICEP).Yamagata, Japan:IEEE, 2017:302-305.
[2]
CHEN J, LIU C T. Technology Advances in Flexible Displays and Substrates[J]. IEEE Access, 2013(1):150-158.
[3]
LU H, TAKAGI Y, SUZUKI Y, et al. Demonstration of 3-5 μm RDL line lithography on panel-based glass interposers[C]// 2014 IEEE 64th Electronic Components and Technology Conference (ECTC).Orlando,FL,USA:IEEE, 2014: 1416-1420.
[4]
TOPPER M, NDIP I, ERXLEBEN R, et al. 3-D Thin film interposer based on TGV (Through Glass Vias):An alternative to Si-interposer[C]// 2010 Proceedings 60th Electronic Components and Technology Conference (ECTC). Las Vegas,NV,USA:IEEE, 2010: 66-73.
[5]
SHI T, BUCH C, SMET V, et al. First Demonstration of Panel Glass Fan-Out (GFO) Packages for High I/O Density and High Frequency Multi-chip Integration[C]// 2017 IEEE 67th Electronic Components and Technology Conference (ECTC).Orlando,FL,USA:IEEE, 2017: 41-46.
[6]
ERIK JUNG, OSTMANN A, WIEMER M, et al. Soldered sealing process to assemble a protective cap for a MEMS CSP[C]// Symposium on Design,Test,Integration and Packaging of MEMS/MOEMS 2003.Cannes,France:IEEE, 2003:255-260.
[7]
SZEPESI Z. Photoconductor-electroluminescent display panels on Fotoform glass[C]// 1962 IEEE International Solid-State Circuits Conference.Digest of Technical Papers.Philadelphia,PA, USA:IEEE, 1962:86-87.
[8]
IIDA H, SHIBA N, MISHUKU T, et al. High efficiency a-Si:H p-i-n solar cell using a SnO2 /glass substrate[J]. IEEE Electron Device Letters, 1982, 3(5):114-115.
[9]
NARAYAN C, PURUSHOTHAMAN S. Thin film transfer process for low cost MCM’s[C]//Proceedings of 15th IEEE/CHMT International Electronic Manufacturing Technology Symposium. Santa Clara,CA, USA:IEEE, 1993:373-380.
[10]
LENHART A, HULSING H. Particle-detection on glass substrates and thin film magnetic storage disks[J]. IEEE Transactions on Magnetics, 1990, 26(1):138-140.
[11]
LEE B, HIRAYAMA Y, KUBOTA Y, et al. A CPU on a glass substrate using CG-silicon TFTs[C]// 2003 IEEE International Solid-State Circuits Conference, 2003.Digest of Technical Papers. ISSCC:Vol. 1. San Francisco,CA,USA: IEEE, 2003:164-165.
[12]
KOHLI J T, LABORDE P. Glasses for display panels: US5854152A[P].1998-12-29.
[13]
KOHLI J T. Glasses for display panels and photovoltaic devices:US6060168A[P].2000-05-09.
[14]
BORRELLI N F, LUONG J C, SACHENIK P A. Method for providing high-intensity optical patterns in glass: US4778744A[P].1988-10-18.
[15]
ARITA T, HIRABAYASHI T. Method for drilling a processed hole to a hard but brittle material and a device therefor:US5285598A[P].1994-02-15.
[16]
HOWARD G J. Drill bit for glass and ceramic structures: US4483108A[P].1984-11-20.
[17]
ANDERSON J G, GILES E Q. Method for forming a glass article possessing an aperture:US6134919A[P].2000-10-24.
[18]
GLESKOVA H, WAGNER S, ZHANG Q, et al. Via hole technology for thin-film transistor circuits[J]. IEEE Electron Device Letters, 1997, 18(11):523-525.
[19]
MOFFATT D M, NEUBAUER D V. Glasses for flat panel display:US5489558A[P].1996-02-06.
[20]
FRANCIS G L. Fusion sealing materials:US5089445A[P].1992-02-18.
[21]
ESASHI M, URA N, MATSUMOTO Y. Anodic bonding for integrated capacitive sensors[C]//Proceedings IEEE Micro Electro Mechanical Systems.Travemunde, Germany:IEEE, 1992:43-48.
[22]
CARRIER G, FRANCIS G L, PAISLEY R J, et al. New TCE-matched glass-ceramic multi-chip module. II. Materials,mechanical,and thermal aspects[C]// Proceedings., 39th Electronic Components Conference.Houston,TX,USA:IEEE, 1989:652-655.
[23]
WHITE G, PERFECTO E, MCHERRON D, et al. Large format fabrication-a practical approach to low cost MCM-D[J]. PART B, 1995, 18(1).
[24]
TAKAHASHI K, TAGUCHI Y, TOMISAKA M, et al. Process integration of 3D chip stack with vertical interconnection[C]// 2004 Proceedings. 54th Electronic Components and Technology Conference (IEEE Cat. No. 04CH37546).Las Vegas,NV,USA:IEEE, 2004:601-609.
[25]
MENDES P M, POLYAKOV A, BARTEK M, et al. Design of a folded-patch chip-size antenna for short-range communications[C]// 33rd European Microwave Conference Proceedings (IEEE Cat. No.03EX723C).Munich,Germany:IEEE, 2003:723-726.
[26]
HUTT D A, WILLIAMS K, CONWAY P P, et al. Challenges in the Manufacture of Glass Substrates for Electrical and Optical Interconnect[C]// 2006 1st Electronic Systemintegration Technology Conference.Dresden,Germany:IEEE, 2006: 1279-1285.
[27]
HERMAN P R, YICK A, LI J, et al. F/sub 2/-laser micromachining of microfluidic channels and vias for biophotonic chip applications[C]// Lasers and Electro-Optics,2003.CLEO '03. Conference on.IEEE, 2003.DOI:10.1109/CLEO.2003.238830.
[28]
TAE HOON KIM, JONG YEOL JEON, YUN PYO KWAK, et al. Interconnection via technology and wafer level package for crystal unit device[C]// 2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT).Penang,Malaysia:IEEE, 2008:1-5.
[29]
SUKUMARAN V, CHEN Q, LIU F, et al. Through-package-via formation and metallization of glass interposers[C]// 2010 Proceedings 60th Electronic Components and Technology Conference (ECTC).Las Vegas,NV,USA:IEEE, 2010: 557-563.
[30]
HU D C, HUNG Y P, CHEN Y H, et al. Embed glass interposer to substrate for high density interconnection[C]// 2014 IEEE 64th Electronic Components and Technology Conference (ECTC). Orlando,FL,USA:IEEE, 2014: 360-364.
[31]
LIU F, NAIR C, SUNDARAM V, et al. Advances in embedded traces for 1.5 μm RDL on 2.5D glass interposers[C]// 2015 IEEE 65th Electronic Components and Technology Conference (ECTC).San Diego,CA:IEEE, 2015: 1736-1741.
[32]
UR REHMAN M, RAVICHANDRAN S, WATANABE A O, et al. Characterization of ABF/Glass/ABF Substrates for mmWave Applications[J]. IEEE Transactions on Components,Packaging and Manufacturing Technology, 2021, 11(3):384-394.
[33]
MA Q, TRAN Q A, SANKMAN R L, et al. Glass core substrate for integrated circuit devices and methods of making the same:US8207453B2[P].2012-06-26.
[34]
BHARATH K, ELSHERBINI A. Integrated magnetic core inductors on glass core substrates:US20200005989A1[P].2020-01-02.
[35]
MARIN B C, PIETAMBARAM S, NAD S, et al. High-permeability thin films for inductors in glass core packaging substrates: US20220406736A1[P].2022-12-22.
[36]
MAHAJAN R V, NEKKANTY S, PIETAMBARAM S V, et al. Microelectronic structure including die bonding film between embedded die and surface of substrate cavity, and method of making same:US20230317619A1[P].2023-10-05.
[37]
PIETAMBARAM S V, DARMAWIKARTA K, IBRAHIM T A, et al. Glass core architectures with dielectric buffer layer between glass core and metal vias and pads: US20230395445A1[P].2023-12-07.
[38]
YOSHIDA T. Wiring board provided with through electrode, method for manufacturing same and semiconductor device:US20160079149A1[P].2016-03-17.
[39]
UMEMURA Y, KOBAYASHI A. Package substrate and method of manufacturing the same:US12068210B2[P].2024-08-20.
[40]
Min T H. Glass core substrate and method for manufacturing the same:US20150034377A1[P].2015-02-05.
[41]
KIL M, PARK D. Semiconductor package and method of manufacturing semiconductor package: US20250079248A1[P].2025-03-06.
[42]
CHUNG H, KIM K, LEE C. Semiconductor package and method of manufacturing the same: US20250079424A1[P]. 2025-03-06.
[43]
PETER B. Glass for Advanced Semiconductor Applications: Myths and Opportunities[EB]//Glass Emergence in Advanced Applications - Corning. (2011-11-08).
[44]
RAMKUMAR J, SUDARSAN V, CHANDRAMOULEESWARAN S, et al. Structural studies on boroaluminosilicate glasses[J]. Journal of Non-Crystalline Solids, 2008, 354(15):1591-1597.
[45]
AGC-EN-A1[EB]//AGC EN-A1 Alkali Free Boro-Aluminosilicate Glass. (2025-04-08).
[46]
MCCANN S, SMET V, SUNDARAM V, et al. Experimental and Theoretical Assessment of Thin Glass Substrate for Low Warpage[J]. IEEE Transactions on Components, Packaging and Manufacturing Technology, 2017, 7(2):178-185.
[47]
ZHAI M, SHI H, SWAMINATHAN M, et al. Broadband Characterization of 6G Microelectronics Packaging Materials:EN-A1 Alkali-Free Boroaluminasilicate Glass Substrates[C]// 2023 Conference on Lasers and Electro-Optics Europe & European Quantum Electronics Conference (CLEO/Europe-EQEC). 2023:1.
[48]
Stress Issues in 3D Interconnect Technology Using Through Glass Vias[J]. Journal of Mechanical Engineering, 2022, 58(2):246.
At present, the three-dimensional (3D) interconnection technology based on glass through vias (TGVs) has been applied to integration passive devices, three-dimensional packaging and optoelectronic device integration because of its excellent electrical and optical properties, good mechanical stability and low-cost. However, the thermal stress caused by the mismatch of thermal expansion coefficients among multi-materials structure and the complex structure of TGV would affect the performance and reliability of the device. In view of this, many scholars have carried out relevant studies. The stress issues in 3D interconnect technology using TGVs are reviewed at home and abroad survey. Thermal stress theoretical models are constructed, the mechanism of size and distribution of stress is summarized for the filled and unfilled copper of the TGVs. The local stress concentration would induce serious thermo and mechanical reliability. Secondly, after times of finite element model analysis, it is concluded that filling polymer in the vias would alleviate the residual stress. Finally, put forward some problems to be solved urgently.
[49]
CHIU C P, QIAN Z, MANUSHAROW M J. Bridge interconnect with air gap in package assembly: US8872349B2[P].2014-10-28.
[50]
RODRIGUEZ A, KINNEY C F, PRIOLO M G, et al. Coaxial vias: US10276483B2[P].2019-04-30.
[51]
DARMAWIKARTA K, AYGUN K, MARIN B C, et al. Low insertion loss coaxial through-hole for highspeed input-ouput: US20240006289A1[P].2024-01-04.
[52]
HANNA C, SEIDEMANN G, MESA E D, et al.Glass bridge for connecting dies:EP4254494A1[P].2023-10-04.
[53]
KARHADE O G, SHAN B. Microelectronic structures including bridges:US20220199575A1[P].2022-06-23.
[54]
SHAN B, CHEN H, BAI Y, et al. Glass substrate device with through glass cavity: US20240215269A1[P].2024-06-27.
[55]
Glass substrates help overcome limitations of organic materials by enabling an order of magnitude improvement in design rules needed for future data centers and AI products[EB]// Glass substrates help overcome limitations of organic materials by enabling an order of magnitude improvement in design rules needed for future data centers and AI products. (2023-09-18).
[56]
BCHIR O J, SALAMA I, GURUMURTHY C, et al. Substrates for optical die structures: US7583871B1[P].2009-09-01.
[57]
LIN Z, BAI Y, SHAN B, et al. Optical semiconductor package and method: US20240219656A1[P].2024-07-04.
[58]
YEARY L, BRUSBERG L, KIM C, et al. Co-packaged Optics on Glass Substrates for 102.4 Tb/s Data Center Switches[C]// 2023 IEEE 73rd Electronic Components and Technology Conference (ECTC).Orlando,FL,USA:IEEE, 2023: 224-227.
[59]
OKORO C, JAYARAMAN S, POLLARD S. Monitoring of the Effect of Thermal Shock on Crack Growth in Copper Through-Glass Via Substrates[C]// 2021 IEEE 71st Electronic Components and Technology Conference (ECTC). 2021: 304-309.
[60]
ZHENG H, YIN B, ZHOU K, et al. Temperature-dependent activation energy of electromigration in Cu/porous low-k interconnects[J]. Journal of Applied Physics, 2017, 122(7):074501.
[61]
OKORO C, ALLOWATT T, POLLARD S. Resolving Thermo-Mechanically Induced Circumferential Crack Formation in Copper Through-Glass Vias[C]// 2021 IEEE 71st Electronic Components and Technology Conference (ECTC). 2021: 954-958.
[62]
PAN K, XU J, LAI Y, et al. In-situ temperature-dependent characterization of copper through glass via (TGV)[J]. Microelectronics Reliability, 2022, 129:114487.
[63]
PAN K, YANG J, LAI Y, et al. High-Temperature Constitutive Behavior of Electroplated Copper TGV Through Numerical Simulation[J]. IEEE Transactions on Components,Packaging and Manufacturing Technology, 2023, 13(11):1861-1867.
[64]
OKORO C, PARK A Y, ALLOWATT T, et al. Elimination of Thermo-Mechanically Driven Circumferential Crack Formation in Copper Through-Glass via Substrate[J]. IEEE Transactions on Device and Materials Reliability, 2021, 21(3):354-360.
[65]
WANG H, LAI C, MA B, et al. Failure Mechanisms Investigation of Through Glass via (TGV) Under Thermal Annealing and Shock[C]// 2024 25th International Conference on Electronic Packaging Technology (ICEPT). 2024: 1-6.
[66]
GUNJI K, TAKAGI N, HIBARINO T. Failure detection technique for 2/2um RDL on FOPLP[C]// 2019 IEEE 21st Electronics Packaging Technology Conference (EPTC). 2019: 184-188.
[67]
CHEN L, WANG Q, CAI J, et al. Study of glass metallization and adhesion evaluation for TGV application[C]// 2013 14th International Conference on Electronic Packaging Technology.Dalian,China:IEEE, 2013: 217-220.
[68]
YANG S, LIN Z, HUANG H, et al. Study of metalization on polyimide-coated quartz glass for spatial application[C]// 2022 International Conference on Microwave and Millimeter Wave Technology (ICMMT).Harbin, China:IEEE, 2022:1-3.
[69]
LIN Y J, HSIEH C C, YU C H, et al. Study of the thermo-mechanical behavior of glass interposer for flip chip packaging applications[C]// 2011 IEEE 61st Electronic Components and Technology Conference (ECTC).Lake Buena Vista,FL,USA:IEEE, 2011: 634-638.
[70]
JOHN L. Solder Joint Reliability of Glass Core Substrate Assemblies[EB]//Solder Joint Reliability of Glass Core Substrate Assemblies.(2024-11-26).
PDF(33463 KB)

Accesses

Citation

Detail

Sections
Recommended

/