PDF(9109 KB)
Clock synchronization technology for CT detectors based on TDC feedback
HU Jinhui, YU Xiaodong
Integrated Circuits and Embedded Systems ›› 2025, Vol. 25 ›› Issue (9) : 71-81.
PDF(9109 KB)
PDF(9109 KB)
Clock synchronization technology for CT detectors based on TDC feedback
To improve the clock synchronization performance of the CT detector, this study proposes a clock synchronization method utilizing a Time-to-Digital Converter (TDC) feedback mechanism and presents a complete prototype architecture of the synchronization system. For the first time, the TDC delay measurement technique based on carry chains is introduced into the clock synchronization scenario of CT detectors. A high-resolution delay measurement module is designed, incorporating multi-level comparators and high-precision delay elements to implement the timing scheduling logic. A finite state machine is employed to control the synchronization process, forming a closed-loop feedback synchronization mechanism. Simulation experiments demonstrate that in a complex scenario with 512 channels and a maximum transmission distance of 1.28 m, the system's synchronization precision remains consistently stable within 10 ps. This represents a remarkable two-order-of-magnitude improvement compared to conventional solutions. Furthermore, the system can effectively apply dynamic compensation to maintain the 10 ps synchronization precision even in the presence of interference-induced jitter. These advancements significantly elevate the precision and reliability of clock synchronization in CT detector systems.
CT detector / clock synchronization / TDC / delay resolution / FPGA
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