Acceleration scheme for LMS algorithms based on RISC-V

YE Anlong, MA Lingkun, QU Zongyi

Integrated Circuits and Embedded Systems ›› 2025, Vol. 25 ›› Issue (5) : 52-59.

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Integrated Circuits and Embedded Systems ›› 2025, Vol. 25 ›› Issue (5) : 52-59. DOI: 10.20193/j.ices2097-4191.2025.0006
Research Paper

Acceleration scheme for LMS algorithms based on RISC-V

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Abstract

The Least Mean Square algorithm, as a typical adaptive filtering algorithm, has found extensive application in the field of noise suppression. Its implementation is mainly based on general-purpose processors, yet this method suffers from low computational efficiency and performance. The RISC-V architecture, with the advantages of open-source, streamlining, and scalability, is suitable for the implementation of dedicated processors. In this paper, a RISC-V based specialized processor is designed for the LMS algorithm. The customized instruction set F extension is used to process floating point numbers, and MAC instructions are added to the coprocessor to complete the acceleration of the LMS algorithm. The experiment results show that the processor can realize effective noise cancellation, when the input signal-to-noise ratio is 5 dB, the signal-to-noise ratio after noise cancellation is 17.5 dB. When the system uses FPU to execute the LMS algorithm, the number of instruction execution is 220 354, and the execution cycle is 586 221. When this design scheme is used, operating in FPU+MAC mode, the number of instruction execution is 31 621, and the execution cycle is 89 412, demonstrating a remarkable improvement in efficiency.

Key words

RISC-V / coprocessor / LMS / FPU / Hummingbird E203

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YE Anlong , MA Lingkun , QU Zongyi. Acceleration scheme for LMS algorithms based on RISC-V[J]. Integrated Circuits and Embedded Systems. 2025, 25(5): 52-59 https://doi.org/10.20193/j.ices2097-4191.2025.0006

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