Neural ordinary differential equation (ODE) network inference in Von Neumann architectures faces problems like the "power wall" and "memory wall". Traditional in-memory computing architectures also suffer from excessive time and power consumption due to numerous digital-to-analog and analog-to-digital conversions. To address these issues, we propose a fully analog compute-in-memory architecture for Neural ODEs based on RRAM to achieve fully analog data flow in network inference. The simulation is completed on the Cadence Virtuoso platform, which includes RRAM device, array, and the peripheral circuits. The test is performed on a 40 nm RRAM test platform and differential input/output PCB, achieving functional verification of the entire system. Experiments and evaluations of the classification tasks of Neural ODEs are conducted with testing errors, ultimately proving the functionality and reliability of the architecture. This lays a solid foundation for subsequent hardware implementation and application deployment.