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Figure/Table detail
Low supply voltage time-domain comparators for low power analog-to-digital converters
LAN Hongjian, YANG Jianhang, WANG Linwei, LI Zhen, ZHOU Rong, LIU Shubin
Integrated Circuits and Embedded Systems
, 2024, 24(
8
): 7-13. DOI:
10.20193/j.ices2097-4191.2023.0007
Fig. 4
Principle of SR latch
Other figure/table from this article
Fig. 1
Circuit diagram of traditional voltage domain comparator
Fig. 2
Traditional time domain comparator structure
Fig. 3
The proposed time domain comparator structure
Fig. 5
The proposed TA circuit diagram
Fig. 6
The comparison of phase accumulation speed between the proposed time domain comparator and traditional comparators
Fig. 7
The proposed on-chip clock source and phase detector circuit diagram
Fig. 8
The proposed time domain comparator core layout
Fig. 9
The proposed time domain comparator output response diagram
Fig. 10
The proposed time domain comparator power consumption curve with frequency variation
Fig. 11
The proposed time domain comparator power consumption distribution map
Fig. 12
Monte Carlo simulation of the offset voltage of a time domain comparator
Table 1
Performance summary
Table 2
Delay and power consumption of comparators under different PVTs