Aerospace integrated circuits are the core foundation technology of aerospace engineering,and their long-term sustained development is crucial for China's progress towards becoming a space power.This article introduces the development status of international integrated circuits,the development trends of aerospace integrated circuits,the development strategies of United States and Europe regarding aerospace integrated circuits,as well as the current development situation of China's aerospace integrated circuits.It elaborates on several considerations for the development of China's aerospace integrated circuits.

Single-photon imaging technology involves multiple aspects such as semiconductor processes,optoelectronic devices,and integrated circuit design.Based on single-photon avalanche diodes,single-photon imaging technology offers high dynamic two-dimensional grayscale imaging,high-precision three-dimensional imaging,and fluorescence lifetime imaging capabilities.It has significant application prospects in fields such as security surveillance,autonomous driving,and biomedicine.With the rapid development of semiconductor process technology,single-photon imaging technology is expected to become a widely used next-generation visual perception technology.This article provides a systematic introduction to imaging technology based on single-photon avalanche diodes,including the device structure of single-photon avalanche diodes,key circuits involved in single-photon imaging,and the latest research progress in gray scale and temporal resolution single-photon image sensors.

To evaluate the single event effects vulnerability of electronic systems being used in space environment,and verify the effectiveness of system-level hardening methods against radiation,this article conducts relevant research on system level single event effect testing methods.Feasibility of irradiating devices in electronic systems one by one under laboratory environment to evaluate single event functional interrupt rate is confirmed.It is suggested that many methods could be used to get the vulnerability data of devices.The procedure to directly sum up the cross section value corresponding to each device is pointed out to be not reasonable.Through all the above suggestions,it is able to support the test for system-level single event effects.

Chiplet integrates multiple small chips into a system chip,aiming to achieve various goals such as chip reusability,heterogeneous integration,performance enhancement,and cost reduction.The development trends of the Chiplet primarily encompass heterogeneous integration,innovative interconnects,and advanced packaging.Notably,interface interconnection is the key of Chiplet technology.Interconnection using the design of physical layer interfaces and data transmission protocols,considering factors like process,packaging techniques,power constraints,and requirements of upper-level applications.Serial and parallel interconnects are two choices for chip-to-chip physical layer interfaces,each with its own advantages and application scenarios.Additionally,for different propagation media,emerging interconnect technologies such as optical and wireless interconnects offer higher bandwidth,lower power consumption,and more flexible interconnection topologies.Chiplet is promising to bring significant breakthroughs and advancements to the field of electronics,promoting more efficient,flexible,and innovative chip design and manufacturing.

An investigation on radiation-hardened technology of single event effect(SEE)for power MOSFETs is described in the paper.In order to decrease the gain of the parasitic bipolar junction transistor (BJT),an optimized reversed-body implant process is utilized.Meanwhile,a variable-doping buffer of epitaxy is designed to reduce the gradient of vertical electric-field,leading to a decreased accumulation of carriers nearly the sensitive gate area.Results show under rated Vds and 15 V negative Vgs bias,the single event burnout (SEB) and single event gate rupture (SEGR) LET of radiation-hardened MOSFETs is above 75 MeV·cm²/mg.Under the same radiation condition,the negative gate-source bias of radiation-hardened MOSFETs reaches to 15~17 V.There is an obvious increase comparing to the unhardened MOSFETs of 7~10 V.

Computing-in Memory (CIM) is an emerging architecture to alleviate "memory walls" and "power consumption walls".With further expansion of the imbalance between CPU processing speed and memory access speed,structures that separate the central process and memory,such as the Von Neumann architecture,lose its superiority.CIM proposes a novel structure that combines the compute unit and the storage to reduce data movement,significantly improving computational efficiency.MRAM,as one of the most promising next-generation nonvolatile memory devices,is also considered a strong candidate for building efficient CIM architectures.CIM based on MRAM can be divided into analog MRAM CIM and digital MRAM CIM according to the different calculation processes.Digital MRAM CIM can be further divided into MRAM write-type CIM,MRAM read-type CIM,and MRAM near memory computing (MRAM NMC) based on how digital logic is generated.Analog MRAM CIM utilizes high parallelism to amortize energy consumption,which has unparalleled advantages in throughput and energy efficiency per unit area compared to digital CIM.However,It is also limited due to its susceptibility to PVT and other characteristics.The implementation methods of digital MRAM CIM are diverse,and write-type CIM almost eliminates data movement outside the memory.Although the flip energy consumption and delay required by the current process of MRAM are too large,which leads to this method staying in the simulation,it does not hinder that write-type CIM is one of the most effective means to alleviate the "memory wall".Read-type CIM relies on the functional design of read amplifiers which has severe limitations,but there still have some developments in the related field.NMC method is an optimal solution that combines the advantages of MRAM nonvolatile devices and CMOS circuits,though there are significant differences in speed and computational energy efficiency between this two devices,and has achieved significant benefits in practical applications.

Silicon-based optoelectronic technology combines the advantages of high integration of large-scale IC manufacturing technology with the advantages of large bandwidth,high speed ability of optoelectronic chips,and promotes the wide application of silicon-based optoelectronic devices in high energy physics experiments,medical imaging and high energy particle colliders.However,photodetectors used in space environment and medical detectors are expected to be subjected to a cumulative fluences of ~10¹² particles/cm² during their operating cycle,while detectors used in large particle colliders are expected to a radiation fluences of ~10¹⁴ particles/cm².In this paper,the advance in space radiation effects of Si-based photodetectors is described in detail,including the radiation effects of Si-based photodiodes,avalanche photodiodes,single photon detectors and photomultiplier after irradiation by different particles.The research results show that the hardness of total ionizing dose for the detector is good,and the displacement damage is the main reason for the degradation of detectors’ key parameters.Due to the difference in working principle,all kinds of devices show different degradation behavior and degradation mechanism in the space radiation.

As the size of semiconductor technology gradually approaches the physical limit,the progress of process technology has led to a decreasing improvement in the power consumption,area,and other performance of chips,semiconductor technology has entered the “post-Moore era”.In order to further meet the high bandwidth communication needs brought about by the rapid development of machine learning,artificial intelligence,and other information and communication industries,Chiplet technology which based on advanced interconnection and packaging techniques,steps into the picture.Chiplet technology disassembles the original complex multifunctional SoC chip into small chips with small area,low cost,and different process nodes,and assembles them through advanced packaging technology,which has received high attention from academia and industry due to its advantages of high yield,low cost,high integration,strong performance,good flexibility,and fast time-to-market.This paper summarizes and elaborates on the technical characteristics,advantages,development history,and specific applications of Chiplet.Meanwhile,the core technologies of Chiplet,especially Chiplet D2D interconnect technology,are introduced in detail.Finally,the existing technical issues and challenges of Chiplet are described,and the suggestions for future development are put forward.

Facing the challenge of the "area wall" in chip design,there is a significant increase in chip manufacturing costs.The chiplet technology enables the production of small area chips using a mature process,and composing by advanced packaging techniques,which can overcome the limitations imposed by the area wall,facilitating agile chip design and reducing overall design costs.Determining an optimal chiplet particle size to meet flexible chip design requirements remains a crucial issue when utilizing chiplet technology.Furthermore,achieving interconnectivity between functional chiplets after dividing chip functions is pivotal for realizing the final functionality of the chip.Therefore,this paper provides a comprehensive review of recent research on chiplet function division,spatial exploration in chiplet design and the influence of chiplet function division on the inter-chip interconnect,while also pointing out that chipet design methodology is an important research direction for the development of chiplet technology in the future.

A single-event burnout (SEB) hardened design based on N-type lateral double-diffused metal-oxide-silicon (NLDMOS) devices with a Nbuffer layer is proposed in this paper.The electrical and single-event characteristics of NLDMOS is verified by TCAD simulation.Without changing the device performance,the 18 V NLDMOS SEB trigger voltage increases from 22 V to 32 V,reaching the theoretical maximum,which is the avalanche breakdown voltage of the device.The NLDMOS device with an Nbuffer structure can suppress the peak electric field transfer when the parasitic bipolar transistor is turned on due to single paricle incident,and avoid avalanche breakdown of the device causing SEB.Furthermore,Nbuffer is also suitable for SEB hardening of 18~60 V NLDMOS.

In high-speed wireline communication,clock-forwarding receivers requires the de-skew circuit to achieve the optimal sampling relationship between the clock and the data,and to ensure the synchronization of multiple data channels.A global de-skew scheme is proposed in the paper,which only uses one data and clock channel for alignment,and implements multi-channel data synchronization by clock delay matching and distribution techniques,reducing the power and area overhead by the independent de-skew circuit for each channel.The proposed receiver consists of 8 data channels,1 half-rate forwarded clock channel,and a global de-skew circuit based on the delay-locked loop.Based on 180 nm CMOS technology,at a data rate of 2.5 Gb/s,it can remove any skew between the input clock and data,and obtain the sampling phase at the center of the data eye,with the ability of clock duty cycle calibration.At a supply voltage of 1.8 V,the total power consumption of the proposed receiver is 187 mW,occupying the area of 0.16 mm²,saving 45.2% and 62.8% of power and area overhead,respectively,compared with the independent de-skew scheme for each channel.

In response to the current issues of inaccurate positioning and easy loss during the tracking process of mobile robots' moving targets,an embedded technology based moving target control and automatic tracking system is designed.This system simulates moving targets with light spots,which can not only control the motion trajectory of the moving target,but also achieve automatic tracking of its motion trajectory.This design takes the embedded chip STM32F103 as the core,processes image data through OpenMV,and adjusts the servo with precise PID algorithm to control the laser pen's spot to move and track on the screen according to the set program.After testing,the system can accurately complete the tracking and automatic tracking tasks of moving targets,with sensitive response and high cost-effectiveness.It can be widely used in intelligent control devices such as moving target tracking.

The reliability of ULSI/VLSI integrated circuit chips is related to both design and process. In order to make the chip of ULSI/VLSI operate stably during a specific lifetime, it is necessary to evaluate the inherent failure mechanism that affects the reliability of chips. The purpose of the evaluation is to determine the mechanism of technical wear and ensure that the chip has good reliability throughout the product life by improving the design and process processing level. This paper reviews the reliability evaluation standards of inherent failure mechanisms at home and abroad, expounds these inherent mechanisms, summarizes the experiment methods of different inherent failure mechanisms, and puts forward the reliability evaluation requirements of inherent failure mechanisms. The reliability evaluation of failure mechanisms play a role in process development, library construction and engineering services, and will promote the development of domestic qualitied manufacturer certification.

With the development of integrated circuits to the Beyond Moor era,the heterogeneous integration technology has become an emerging direction of microelectronics.The interconnect interface,the key to the heterogeneous integration technology, is critical to heterogeneous integrated chip and system.In order to promote the implementation of heterogeneous integrated interconnect interface, the structure of the heterogeneous integrated chip and system is described and the heterogeneous integration technology is summarized into four technical routes:large chip by integrated chiplets, larger chip by integrated large chips,wafer-level chips and wafer-level systems. The characteristics of the heterogeneous integrated interconnect interface are summarized.The current research status and existing problems in the industry and academia around the heterogeneous integrated interconnect interface are analyzed.Finally,the future development trend and the needed technical characteristics of the heterogeneous integrated interconnect interface are given by this article.

Miniaturization of chip/system dimensions and functional composites have led to an increase in power density, accompanied by the growth in heat generation. Addressing this problem has become a great challenge in thermal design and a current research hotspot. This paper discusses the advantages and disadvantages of traditional heat dissipation techniques, and systematically analyzes the embedded microchannel heat dissipation structures at home and abroad. The article focuses on summarizing the principles, thermal performance and innovative solutions of heat dissipation technology based on embedded microchannel chips. Current domestic and international solutions are analyzed, and we summarize the experiences and conclusions of chip thermal design based on embedded microchannels, along with the challenges faced. Finally, the current status and future directions of chip thermal design research are presented.

As one of the most advanced new high-density packaging processes, TSV has an extremely complex structural process. Currently, there are few quality inspection and reliability evaluation methods for large-scale applications and engineering applications in China, and relevant unified standards have not been fully established. This paper focuses on TSV silicon interposers in 2.5D packaging, which are the relatively mature and reach the industry consensus. Combining its process structure characteristics and front-line data from actual product production testing, the quality inspection method and the reliability evaluation method for TSV silicon interposers based on the forward movement of quality assurance are studied. A mature solution is established for the process quality monitoring, inspection evaluation, reliability assurance, and the establishment of related standards and specifications for TSV process products.

The I²C bus is widely employed for exchanging data between multiple chips and modules in embedded systems.However,the utilization of dedicated I²C bus pins has limitations when these pins are already occupied or when the I²C bus function needs to be migrated to other platforms.In the study,a driver program is developed that leverages the communication mechanism of the I²C bus.It achieves I²C bus communication functionality by simulating I²C timing through the control of electrical levels on conventional GPIO pins.The STM32F103C8T6 chip serves as the primary controller of the I²C bus,while the PCF8591T A/D conversion module operates as the slave device.This article verifies the developed I²C driver program,and the experimental results show that the driving method is reliable and stable.

Aiming at the problems of increasing additional hardware overhead and sacrificing loading speed in the existing embedded OS loading mode selection method,an embedded OS loading mode selection method based on link state information is proposed.The method utilizes the reset of PHY and other peripherals after power-on and then reset the CPU,which runs the BootLoader to read and judge the link establishment signal of PHY to determine the loading mode,and if the link establishment signal indicates that the network has been connected,the Ethernet remote loading mode will be selected,while the local memory loading mode will be selected in all other cases.The results of engineering application show that the proposed method is stable and reliable.