Aerospace integrated circuits are the core foundation technology of aerospace engineering,and their long-term sustained development is crucial for China's progress towards becoming a space power.This article introduces the development status of international integrated circuits,the development trends of aerospace integrated circuits,the development strategies of United States and Europe regarding aerospace integrated circuits,as well as the current development situation of China's aerospace integrated circuits.It elaborates on several considerations for the development of China's aerospace integrated circuits.

Miniaturization of chip/system dimensions and functional composites have led to an increase in power density, accompanied by the growth in heat generation. Addressing this problem has become a great challenge in thermal design and a current research hotspot. This paper discusses the advantages and disadvantages of traditional heat dissipation techniques, and systematically analyzes the embedded microchannel heat dissipation structures at home and abroad. The article focuses on summarizing the principles, thermal performance and innovative solutions of heat dissipation technology based on embedded microchannel chips. Current domestic and international solutions are analyzed, and we summarize the experiences and conclusions of chip thermal design based on embedded microchannels, along with the challenges faced. Finally, the current status and future directions of chip thermal design research are presented.

Single-photon imaging technology involves multiple aspects such as semiconductor processes,optoelectronic devices,and integrated circuit design.Based on single-photon avalanche diodes,single-photon imaging technology offers high dynamic two-dimensional grayscale imaging,high-precision three-dimensional imaging,and fluorescence lifetime imaging capabilities.It has significant application prospects in fields such as security surveillance,autonomous driving,and biomedicine.With the rapid development of semiconductor process technology,single-photon imaging technology is expected to become a widely used next-generation visual perception technology.This article provides a systematic introduction to imaging technology based on single-photon avalanche diodes,including the device structure of single-photon avalanche diodes,key circuits involved in single-photon imaging,and the latest research progress in gray scale and temporal resolution single-photon image sensors.

Chiplet integrates multiple small chips into a system chip,aiming to achieve various goals such as chip reusability,heterogeneous integration,performance enhancement,and cost reduction.The development trends of the Chiplet primarily encompass heterogeneous integration,innovative interconnects,and advanced packaging.Notably,interface interconnection is the key of Chiplet technology.Interconnection using the design of physical layer interfaces and data transmission protocols,considering factors like process,packaging techniques,power constraints,and requirements of upper-level applications.Serial and parallel interconnects are two choices for chip-to-chip physical layer interfaces,each with its own advantages and application scenarios.Additionally,for different propagation media,emerging interconnect technologies such as optical and wireless interconnects offer higher bandwidth,lower power consumption,and more flexible interconnection topologies.Chiplet is promising to bring significant breakthroughs and advancements to the field of electronics,promoting more efficient,flexible,and innovative chip design and manufacturing.

As the size of semiconductor technology gradually approaches the physical limit,the progress of process technology has led to a decreasing improvement in the power consumption,area,and other performance of chips,semiconductor technology has entered the “post-Moore era”.In order to further meet the high bandwidth communication needs brought about by the rapid development of machine learning,artificial intelligence,and other information and communication industries,Chiplet technology which based on advanced interconnection and packaging techniques,steps into the picture.Chiplet technology disassembles the original complex multifunctional SoC chip into small chips with small area,low cost,and different process nodes,and assembles them through advanced packaging technology,which has received high attention from academia and industry due to its advantages of high yield,low cost,high integration,strong performance,good flexibility,and fast time-to-market.This paper summarizes and elaborates on the technical characteristics,advantages,development history,and specific applications of Chiplet.Meanwhile,the core technologies of Chiplet,especially Chiplet D2D interconnect technology,are introduced in detail.Finally,the existing technical issues and challenges of Chiplet are described,and the suggestions for future development are put forward.

The reliability of ULSI/VLSI integrated circuit chips is related to both design and process. In order to make the chip of ULSI/VLSI operate stably during a specific lifetime, it is necessary to evaluate the inherent failure mechanism that affects the reliability of chips. The purpose of the evaluation is to determine the mechanism of technical wear and ensure that the chip has good reliability throughout the product life by improving the design and process processing level. This paper reviews the reliability evaluation standards of inherent failure mechanisms at home and abroad, expounds these inherent mechanisms, summarizes the experiment methods of different inherent failure mechanisms, and puts forward the reliability evaluation requirements of inherent failure mechanisms. The reliability evaluation of failure mechanisms play a role in process development, library construction and engineering services, and will promote the development of domestic qualitied manufacturer certification.

Computing-in Memory (CIM) is an emerging architecture to alleviate "memory walls" and "power consumption walls".With further expansion of the imbalance between CPU processing speed and memory access speed,structures that separate the central process and memory,such as the Von Neumann architecture,lose its superiority.CIM proposes a novel structure that combines the compute unit and the storage to reduce data movement,significantly improving computational efficiency.MRAM,as one of the most promising next-generation nonvolatile memory devices,is also considered a strong candidate for building efficient CIM architectures.CIM based on MRAM can be divided into analog MRAM CIM and digital MRAM CIM according to the different calculation processes.Digital MRAM CIM can be further divided into MRAM write-type CIM,MRAM read-type CIM,and MRAM near memory computing (MRAM NMC) based on how digital logic is generated.Analog MRAM CIM utilizes high parallelism to amortize energy consumption,which has unparalleled advantages in throughput and energy efficiency per unit area compared to digital CIM.However,It is also limited due to its susceptibility to PVT and other characteristics.The implementation methods of digital MRAM CIM are diverse,and write-type CIM almost eliminates data movement outside the memory.Although the flip energy consumption and delay required by the current process of MRAM are too large,which leads to this method staying in the simulation,it does not hinder that write-type CIM is one of the most effective means to alleviate the "memory wall".Read-type CIM relies on the functional design of read amplifiers which has severe limitations,but there still have some developments in the related field.NMC method is an optimal solution that combines the advantages of MRAM nonvolatile devices and CMOS circuits,though there are significant differences in speed and computational energy efficiency between this two devices,and has achieved significant benefits in practical applications.

The combination of Robots and artificial intelligence will lead the transformation of new intelligent technologies. Furthermore, as a crucial component of artificial intelligence, neural networks demonstrate immense potential in robotic perception. However, the increasing complexity of AI algorithms and the prominent energy efficiency bottleneck of general-purpose processors such as CPUs pose significant challenges. Traditional processing chips fail to effectively accommodate the inference computing tasks of large-scale neural networks. In recent years, robotic AI chips, with high computing performance and low power consumption, have emerged as an ideal choice for deploying of neural networks in robot systems due to their, attracting widespread attention. This article focusing on robotic applications, studies the current status of AI algorithms, reviews the latest advances in AI chip design technology, proposes technical difficulties and feasible technical routes, and discusses the technical trends and challenges in the design of robotic AI chips.

Facing the challenge of the "area wall" in chip design,there is a significant increase in chip manufacturing costs.The chiplet technology enables the production of small area chips using a mature process,and composing by advanced packaging techniques,which can overcome the limitations imposed by the area wall,facilitating agile chip design and reducing overall design costs.Determining an optimal chiplet particle size to meet flexible chip design requirements remains a crucial issue when utilizing chiplet technology.Furthermore,achieving interconnectivity between functional chiplets after dividing chip functions is pivotal for realizing the final functionality of the chip.Therefore,this paper provides a comprehensive review of recent research on chiplet function division,spatial exploration in chiplet design and the influence of chiplet function division on the inter-chip interconnect,while also pointing out that chipet design methodology is an important research direction for the development of chiplet technology in the future.

In high-speed wireline communication,clock-forwarding receivers requires the de-skew circuit to achieve the optimal sampling relationship between the clock and the data,and to ensure the synchronization of multiple data channels.A global de-skew scheme is proposed in the paper,which only uses one data and clock channel for alignment,and implements multi-channel data synchronization by clock delay matching and distribution techniques,reducing the power and area overhead by the independent de-skew circuit for each channel.The proposed receiver consists of 8 data channels,1 half-rate forwarded clock channel,and a global de-skew circuit based on the delay-locked loop.Based on 180 nm CMOS technology,at a data rate of 2.5 Gb/s,it can remove any skew between the input clock and data,and obtain the sampling phase at the center of the data eye,with the ability of clock duty cycle calibration.At a supply voltage of 1.8 V,the total power consumption of the proposed receiver is 187 mW,occupying the area of 0.16 mm²,saving 45.2% and 62.8% of power and area overhead,respectively,compared with the independent de-skew scheme for each channel.

To address the demands of digital acquisition of vital signs signals and continuous blood pressure prediction,this paper designs and constructs a continuous blood pressure prediction system based on two-dimensional (2D) convolution.The system hardware adopts ESP32 module,AD8232 module and PulseSensor sensor to collect the human electrocardiography (ECG) and photoplethysmography (PPG) signal data,which are then transmitted to the server through the MQTT protocol for the consequent processing.Regarding the algorithms of this paper,a neural network model using ECG and PPG signals was designed and trained to predict continuous human blood pressure,employing the Gramian angular difference field (GADF),2D convolution,and model pruning techniques.The performance of the continuous blood pressure prediction model is verified on both classic open-source datasets and self-collected datasets.This system proposed in this paper provides a practical reference scheme for the vital signs signal acquisition and continuous blood pressure prediction.

Transient circuit simulations often necessitate the construction of linear system models,where the sequential solution of triangular matrices with multiple right-hand terms becomes a time-intensive process.To expedite the computational efficiency of back-substitution for these matrices in transient circuit simulations,this paper proposes a parallel computing method based on a heterogeneous platform.The method prioritizes the computation of multiplications relevant to the solution vector,exploiting the inherent parallelism of back-substitution calculations.The architecture features a core operation array with multiple floating-point calculation units and a control module employing a two-tiered master-slave state machine.Using the Zynq UltraScale series FPGA,specifically the XCZU15EG model,our architecture is compared to an Intel 24-core CPU platform utilizing the MKL solving library in linear matrix resolution experiments.The matrices used exhibit characteristics of being symmetric positive definite,diagonally dominant,and dense with a sparsity exceeding 50%.The proposed acceleration architecture achieves an average speedup factor of 22,with solution errors falling within the range of 10^-17 to 10^-14.The experiment results demonstrate the architecture's significant enhancement of matrix solution speed,especially suitable for forward and backward substitution resolution of high-dimensional linear matrices in transient circuit simulations.

High-speed extra short reach (XSR) wireline interfaces are an important technical solution for chiplets interconnection.The traditional continuous time linear equalizer (CTLE) based on current mode logic (CML) has gradually failed to meet the demand for high-density,miniaturization,and low-power consumption of chiplet data interfaces due to the use of high supply voltage and passive components.To address this problem,this paper proposes an inverter-based CTLE with mid-frequency compensation (MFC) to transmit 28 Gb/s non-return to zero (NRZ) signals as well as 56 Gb/s 4-level pulse amplitude modulation (PAM4) signals in XSR applications.The design is implemented in a 28 nm CMOS process with a core area of only 400 μm².After an XSR channel at -9.4 dB@14 GHz,the post-layout simulation results show that the proposed CTLE improves the eye width of the 28 Gbaud NRZ and PAM4 signals by 0.14 UI and 0.41 UI,and the eye heights by 328 mV and 119 mV,respectively.The power consumption is 6.12 mW at 56 Gb/s PAM4 signaling.

Aiming at the current problems of high power consumption and high cost performance of image acquisition devices for embedded devices,a low-cost and low-power real-time system design program is proposed.In the hardware design,OV2640 CMOS sensor is used as the acquisition front-end,CH565W chip is used as the main control chip for control and processing,and RTL8211FS is used as the Gigabit Ethernet physical layer chip for data transmitting and receiving.For the software design,the image acquisition program with double buffer mode,data transceiver flow and low power management program are introduced.The test results of the system show that the image transmission is clear and smooth,and the power consumption,cost,and real-time performance meet the design requirements.

An investigation on radiation-hardened technology of single event effect(SEE)for power MOSFETs is described in the paper.In order to decrease the gain of the parasitic bipolar junction transistor (BJT),an optimized reversed-body implant process is utilized.Meanwhile,a variable-doping buffer of epitaxy is designed to reduce the gradient of vertical electric-field,leading to a decreased accumulation of carriers nearly the sensitive gate area.Results show under rated Vds and 15 V negative Vgs bias,the single event burnout (SEB) and single event gate rupture (SEGR) LET of radiation-hardened MOSFETs is above 75 MeV·cm²/mg.Under the same radiation condition,the negative gate-source bias of radiation-hardened MOSFETs reaches to 15~17 V.There is an obvious increase comparing to the unhardened MOSFETs of 7~10 V.

To evaluate the single event effects vulnerability of electronic systems being used in space environment,and verify the effectiveness of system-level hardening methods against radiation,this article conducts relevant research on system level single event effect testing methods.Feasibility of irradiating devices in electronic systems one by one under laboratory environment to evaluate single event functional interrupt rate is confirmed.It is suggested that many methods could be used to get the vulnerability data of devices.The procedure to directly sum up the cross section value corresponding to each device is pointed out to be not reasonable.Through all the above suggestions,it is able to support the test for system-level single event effects.

Silicon-based optoelectronic technology combines the advantages of high integration of large-scale IC manufacturing technology with the advantages of large bandwidth,high speed ability of optoelectronic chips,and promotes the wide application of silicon-based optoelectronic devices in high energy physics experiments,medical imaging and high energy particle colliders.However,photodetectors used in space environment and medical detectors are expected to be subjected to a cumulative fluences of ~10¹² particles/cm² during their operating cycle,while detectors used in large particle colliders are expected to a radiation fluences of ~10¹⁴ particles/cm².In this paper,the advance in space radiation effects of Si-based photodetectors is described in detail,including the radiation effects of Si-based photodiodes,avalanche photodiodes,single photon detectors and photomultiplier after irradiation by different particles.The research results show that the hardness of total ionizing dose for the detector is good,and the displacement damage is the main reason for the degradation of detectors’ key parameters.Due to the difference in working principle,all kinds of devices show different degradation behavior and degradation mechanism in the space radiation.

With the development of integrated circuits to the Beyond Moor era,the heterogeneous integration technology has become an emerging direction of microelectronics.The interconnect interface,the key to the heterogeneous integration technology, is critical to heterogeneous integrated chip and system.In order to promote the implementation of heterogeneous integrated interconnect interface, the structure of the heterogeneous integrated chip and system is described and the heterogeneous integration technology is summarized into four technical routes:large chip by integrated chiplets, larger chip by integrated large chips,wafer-level chips and wafer-level systems. The characteristics of the heterogeneous integrated interconnect interface are summarized.The current research status and existing problems in the industry and academia around the heterogeneous integrated interconnect interface are analyzed.Finally,the future development trend and the needed technical characteristics of the heterogeneous integrated interconnect interface are given by this article.

To further optimize the performance of the multiplier and improve the operation speed of the multiplication unit,an improved 16-bit signed number multiplier is designed based on the Radix-4 Booth algorithm and Wallace tree compression structure.Its characteristics are:optimize the Radix-4 Booth encoding method to effectively reduce the area of partial product selection circuits.Improve the partial product calculation process by optimizing the inverse plus one method to directly generate the opposite of the multiplicand,at the same time,use the classic sign bit compensation algorithm to make the partial product array regular and easy to compress.A new type of 4-2 compressor is proposed,which uses a single full adder to process the middle carry of the compressor.The Wallace tree compression structure is refined to improve the compression efficiency of partial products for different data features in each row.Synthesis and verified based on SMIC 180 nm standard cell library,the results show that the critical path delay of the multiplier designed in this paper is 3.94 ns,with an area of 16 246 μm².Compared to existing multipliers,the computational speed and overall performance of the multiplier in this paper have been significantly improved.

As novel non-volatile memory,magneto-resistive random access memory (MRAM) has broad application prospects in the field of embedded memory due to its excellent read and write speed and endurance characteristics.However,since the customized design of MRAM usually takes several months to complete,it requires a long design period,which conflicts with the need for a faster design iteration of the system-on-chip.As a tool for quickly generating memory designs,the memory compiler is an effective means to resolve this contradiction.This article starts with the fully customized design process of magnetic random access memory and conducts a survey on the research status of various types of memory compilers.We summarize the current status and challenges of memory compiler design from published work and finally discuss the design methodology of magnetic random access memory compiler.

Three-dimensional (3D) imaging technology based on Time-of-Flight (ToF) belongs to active 3D imaging technology.It calculates the distance information of the target object by measuring the time needed for modulated light to "fly" back and forth between the target object and the sensor.Compared to other 3D imaging methods, ToF-based 3D imaging methods have significant advantages such as miniaturization, simple structure,and low power consumption.With the development of technology,Indirect Time-of-Flight (IToF) image sensor pixel size gradually decreases,resolution increases,and accuracy improves,making it applicable in various scenarios.However,it still faces challenges such as background light interference,multipath interference,and motion artifacts.The working principle of ToF image sensors is introduced in section 1.The parameter indicators of ToF image sensors and their development trends are analyzed in section 2.The challenges faced by ToF image sensors are analyzed and the solutions are proposed in section 3.The image correction and restoration algorithms applied to ToF technology are introduced in section 4.

With the development of Ethernet technology,the demand for data processing speed in the field of network data exchange is growing.Additionally,the reliability and autonomous controllability of the localized Ethernet interface are becoming increasingly important.In view of this,the QSGMII interface based on FPGA is designed using the top-down method,achieving the required transmission rate of 5 Gbps by the protocol.The design principle and idea of the key modules are described.A new multi-channel arbitration mechanism is proposed in the design,which improves the reuse of SGMII soft core and reduces the complexity of circuit design while ensuring the four-channel alignment.The software simulation of QSGMII interface verifies the correctness of RTL code function.Finally,based on VC709 FPGA development board,single channel data sending and receiving test was performed through network analysis software Wireshark.Xilinx's QSGMII interface core was conneted with the self-developed QSGMII interface for data docking test,realizing the interweaving transmission of four independent SGMII interfaces.

To solve the problems of poor route ability in flexible printed circuit board,a bus planning algorithm based on pattern routing is proposed,which approximates detailed routing and reduces the precision error between detail routing and bus planning.At the same time,four routing patterns and several fan-out strategies are designed according to manual experience to simulate the possible situation of resource allocation in pin area and arrangement combination of pin areas.Besides,a layer assignment algorithm is designed to comprehensively evaluate the current routing results and the future impact on other nets.According to the restriction that vias are not allowed in the channel,the non-intersecting sequence of the routing topology of the nets in the channel is obtained according to the position sequence of pin areas connected with the channel,which is used as the constraint of the arrangement sequence of the points on the boundary line.Finally,the results in each pattern are comprehensively compared,and the least expensive result is selected as the final bus planning result. Experimental results on industrial cases show that the proposed algorithm realize better performance compared with the existing flexible printed circuit board bus planning algorithm.

Aiming at the application requirements of high frame rate CMOS image sensors,a hybrid analog-to-digital converter (ADC) combining successive approximation register (SAR) and single slope (SS) structures is proposed.The resolution of this ADC is 12-bit,with SAR ADC achieving high 6-bit quantization and SS ADC achieving low 6-bit quantization.The ADC adopts a fully differential structure to eliminate fixed misalignment of the sampling switch and reduce nonlinear errors.At the same time,asynchronous logic circuits are used in SAR ADC to further shorten the conversion cycle.The circuit is designed and implemented using 110 nm 1P4M CMOS technology.The post-layout simulation results show that at clock frequency of 20 MHz,the conversion period is only 3.3 μs,the spurious free dynamic range is 77.12 dB,the signal-to-noise distortion ratio is 67.38 dB,and the effective bit is 10.90 bits.

Voting-based classifiers are widely used in many A.pngicial Intelligence (AI) applications.In their implementation,memories that store all known data are prone to suffer different effects like radiation and physical variations,causing soft errors and can even change the classification results.Therefore,error-tolerance must be achieved in these memories for safety-critical applications.Existing error-tolerant techniques commonly utilize error correction codes,however,the memory redundancy they introduce further increases the burden of storage.In this paper,a redundancy-free technique is proposed by focusing on the impact of errors on the classification performance,instead of the error itself.It can recover the error-free classification results under errors by exploiting the flipped data.A k nearest neighbor classifier is taken as a case study to evaluate the proposed technique.The simulation results show that the proposed scheme offers almost full error tolerance without incurring any memory redundancy,moreover,it significantly reduces the hardware overheads for protection circuits compared to existing techniques.

Robots represent a revolutionary engine of new productive forces, reshaping human life and work. Simultaneous Localization And Mapping (SLAM) technology enables robots to navigate autonomously in unknown environments and construct maps of their surroundings, serving as the cornerstone for the intelligence of autonomous mobile robots. However, given that SLAM algorithms are complex and computationally intensive, implementations based on general-purpose CPU chips suffer from long delays and high power consumption, which fails to meet the real-time and power consumption requirements of autonomous mobile robots, especially small, micro, and nano ones. Consequently, the design of specialized hardware accelerator chips to accelerate computation-intensive SLAM algorithms has received considerable attention from both the academic and industrial communities in recent years. This article starts with the basic concepts and application scenarios of SLAM technology, and highlights the necessity of hardware acceleration for SLAM algorithms. It then reviews the current research status and development trends from the perspectives of algorithms and dedicated chip design, and discusses the technical challenges and solutions related to SLAM dedicated chips, providing recommendions for future development.

Currently,analytical methods have achieved the best results for VLSI floorplanning.Module flipping has real applications and can further optimize floorplanning results,but analytical methods cannot handle modules flipping in floorplaning.Therefore,this paper attempts to solve this problem by using a unified analytical method,and proposes a new force,i.e.,the flipping force,for modules flipping.The flipping force can guide each module's flipping to its desired direction based on wire length optimization during the global floorplanning stage.In addition,based on the electrostatic field model,this paper designs a new global floorplanning flow in which special treatment is applied to the density calculation of large-size modules.The aim is to reduce the repulsion of these modules and allow other modules to be placed closer to them,thus achieving a more uniform distribution of modules.To better utilize the whitespace between the floorplan boundary and large modules,a gap handling method is proposed.Finally,a post-floorplanning stage is applied to further optimize the floorplanning result.This stage involves re-optimizing the modules flipping directions using a mixed-integer linear programming,followed by applying our proposed new whitespace redistribution method.The whitespace redistribution method reduces the number of constraints in the linear programming problem and allows multiple rounds of optimization,leading to a more effective reduction of wire length compared to previous methods.The experimental results on HB+ and ami49_x benchmark circuits show that the proposed floorplanning algorithm achieves an average half-perimeter wire length reduction of at least 13.3% and 13.7%,respectively,compared to state-of-the-art floorplanning algorithms.

A single-event burnout (SEB) hardened design based on N-type lateral double-diffused metal-oxide-silicon (NLDMOS) devices with a Nbuffer layer is proposed in this paper.The electrical and single-event characteristics of NLDMOS is verified by TCAD simulation.Without changing the device performance,the 18 V NLDMOS SEB trigger voltage increases from 22 V to 32 V,reaching the theoretical maximum,which is the avalanche breakdown voltage of the device.The NLDMOS device with an Nbuffer structure can suppress the peak electric field transfer when the parasitic bipolar transistor is turned on due to single paricle incident,and avoid avalanche breakdown of the device causing SEB.Furthermore,Nbuffer is also suitable for SEB hardening of 18~60 V NLDMOS.

To address the issues of slow processing speed, low accuracy, and high hardware resource consumption in traditional license plate recognition systems, an efficient license plate recognition system is designed and implemented. This system is based on Field-Programmable Gate Array (FPGA) and Binary Neural Network (BNN) technology. By combining hardware acceleration with algorithm optimization, the system significantly enhances license plate recognition performance. The experimental results show that the system achieves a recognition accuracy of 96.46%, reducing the recognition time to 12 milliseconds. Compared to traditional license plate recognition algorithms and CNN-FPGA solutions, this system demonstrates significant advantages in hardware resource consumption, recognition speed, and accuracy, providing an efficient and resource-friendly solution for license plate recognition.

To address the power waste problems of wireless receiver module in the Internet of Things,a nanowatt wake-up receiver is designed and implemented.The wake-up receiver "wakes up" the main receiver after receiving the wake-up signal.The wake-up receiver system includes matching network,passive envelope detection,baseband amplifier,comparator,correlator and digital comparator.The proposed passive envelope detection replaces the traditional active detection circuit,significantly lowering the system power consumption,while providing 23.6 dB passive gain with the front-end passive matching network.The information is modulated by on-off keying (OOK).The wake up receiver is designed based on 65 nm CMOS technology.Under the carrier frequency of 433 MHz,data rate of 100 bps and code length of 8 bit OOK signal,the sensitivity of the wake up receiver can reach -72 dBm.The power consumption of the analog part is 21.9 nW,and the power consumption of the digital part is 93.8 nW.

The I²C bus is widely employed for exchanging data between multiple chips and modules in embedded systems.However,the utilization of dedicated I²C bus pins has limitations when these pins are already occupied or when the I²C bus function needs to be migrated to other platforms.In the study,a driver program is developed that leverages the communication mechanism of the I²C bus.It achieves I²C bus communication functionality by simulating I²C timing through the control of electrical levels on conventional GPIO pins.The STM32F103C8T6 chip serves as the primary controller of the I²C bus,while the PCF8591T A/D conversion module operates as the slave device.This article verifies the developed I²C driver program,and the experimental results show that the driving method is reliable and stable.

In the paper,a domestic motor drive system is designed based on GD32F407.The system is an important part of the application transfer device of positioning directional navigation system and needs to be used with a turntable.Its main function is to generate excitation signals of angle position sensors,namely rotating transformers.The dedicated modulation and demodulation position information chip is used to accurately judge the rotating position of the motor,the single-chip microcomputer is used to realize signal processing,modulation and demodulation position information processing,and the motor driver chip WSA67 is used to drive the motor to complete directional quantitative rotation of the turntable,and the stable speed control of the turntable is realized in the process of rotation.At the same time,the data transmission with the turntable system is completed through the isolated serial interface.

The monitoring of industrial equipment status is crucial for ensuring production safety and equipment lifespan.To address the challenge of dealing with large volumes of real-time data in industrial equipment status monitoring,a multi-parameter data acquisition system for industrial equipment based on ZYNQ has been designed.This system centers around the ZYNQ7000 series SoC,utilizing IEPE interface sensors and 4~20 mA current loop transmitters to achieve long-distance transmission and minimize interference.The system incorporates sensor signal conditioning circuits,an 8-channel high-speed A/D acquisition module,and a DMA high-speed transmission module.The vibration table and constant temperature box test results demonstrate that this multi-parameter data acquisition system effectively captures industrial equipment status data and transmits it in real-time to the host computer.This aids users in promptly detecting equipment malfunctions and implementing necessary maintenance measures,consequently enhancing equipment availability and production efficiency.

With the increasing integration of printed circuit board,traditional methods are unable to meet the requirements for size and weight.Copper plating,a crucial step in PCB design,plays a significant role in improving the performance and effectiveness of PCB.To address the numerous circular features on large-scale PCB,a fast shape filling algorithm is proposed.This algorithm utilizes graphic information classification and identifies islands that may arise during the copper plating process.The core idea of the algorithm is as follows:firstly,a large number of features are divided into regions based on their graphical information.Then,clustering is performed based on collision relationships.The outer contour chains and isolated island chains are obtained based on the clustering results.Finally,the result is obtained through the relationship between the contour chains of loops and holes.The algorithm is implemented in a Windows 10 environment with a 3.20 GHz processor and 16 GB memory,and industrial test data is used to validate its performance.The experimental results demonstrate that compared to an open-source copper plating tool based on fitting polygons,the proposed algorithm is independent of the number of polygon edges and achieves a time improvement of approximately 60%.

To detect the error occurring during data transmission on the CAN bus as early as possible and fix the failure node promptly, a CAN bus error detection system with FPGA as the core controller is studied and designed. The system uses Verilog HDL to design the CAN controller to realize the parsing function of the CAN bus protocol. Analyzing the types of errors that occur on the bus can detect bit errors, padding errors, validation errors, format errors, and answer errors. The detection results are encapsulated in the UDP data segment in a fixed format and sent to an upper computer for display through the UDP driver. The experiment in simulated CAN communication environment shows that the system can accurately detect the errors on the CAN bus, indicating its potential application value in guaranteeing the stability of the bus communication.

To address issues of large delay and high power consumption in the Successive Approximation Analog-to-Digital Converter (SAR ADC) voltage-domain comparator,a-low-power-time-domain-comparator is designed in this paper.By introducing a high-gain Time Amplifier (TA),the comparator achieved an exponential increase in phase accumulation speed.This effectively reducing the number of oscillation cycles required for the input signal phase to exit the "dead zone" of the phase discriminator,thereby shortening the comparison delay and optimizing the speed and power consumption.The comparator is designed based on a 65 nm CMOS process and consumes only 5.24 nW at 0.4 V supply voltage and 5.99 mV offset voltage.

With the advancement of integrated circuit technology and the increasing operating frequency of circuits,the impact of Multiple-Input Switching (MIS) effects on circuit static timing analysis has become more prominent,exacerbated by process variations.Traditional Single-Input Switching (SIS) timing library construction methods struggle to handle violations of hold time and setup time.In recent years,several MIS delay models have been proposed to characterize the influence of MIS effects in timing analysis.However,most of these models overlook the impact of input switching time and load on MIS effects,resulting in pessimistic and less accurate predictions.Furthermore,these models individually model each unit without considering the relationship between MIS effects and the transistor-level topology of the unit,leading to decreased accuracy and higher characterization costs.To address these challenges,this paper proposes a novel MIS unit delay prediction framework based on heterogeneous graph neural networks.The transistor-level circuitry of multiple-input units is modeled as a heterogeneous graph,providing a comprehensive and effective representation of factors influencing MIS delay.Multiple-input gate MIS effects are trained as a unified model within this framework.In the context of the 16 nm process,the proposed model is validated on multiple-input units.The experiment results indicate that while reducing the modeling cost to 8.8% of the cost required by the ANN model,the model achieves an average error of only 1.19% for units.Compared to the ANN model,the accuracy has improved 2.05 times.

As one of the most advanced new high-density packaging processes, TSV has an extremely complex structural process. Currently, there are few quality inspection and reliability evaluation methods for large-scale applications and engineering applications in China, and relevant unified standards have not been fully established. This paper focuses on TSV silicon interposers in 2.5D packaging, which are the relatively mature and reach the industry consensus. Combining its process structure characteristics and front-line data from actual product production testing, the quality inspection method and the reliability evaluation method for TSV silicon interposers based on the forward movement of quality assurance are studied. A mature solution is established for the process quality monitoring, inspection evaluation, reliability assurance, and the establishment of related standards and specifications for TSV process products.

This study developed a Field-Controlled Enhancement Backside-Illuminated Single-Photon Avalanche Diode (SPAD) device using a simulation design platform. By adjusting the electric field in the avalanche region of the backside-illuminated SPAD, the photon detection efficiency was further improved, and the dark count rate was reduced. Simulation results indicate that the SPAD design effectively enhances electron multiplication efficiency through the synergistic effect of horizontal and vertical electric fields, achieving a peak detection efficiency of 50.1%. At an excess bias voltage of 3V, the dark count rate decreased to 764 Hz. The study compares and analyzes the effects of different depletion layer thicknesses and P-Well radii on the performance of the field-controlled enhanced backside SPAD device, determining the optimal structural dimensions. The results provide a new technical approach for high-precision photoelectric detection applications based on SPAD and lay the groundwork for further development and application of SPAD technology in scientific research and industrial applications.

In response to the current issues of inaccurate positioning and easy loss during the tracking process of mobile robots' moving targets,an embedded technology based moving target control and automatic tracking system is designed.This system simulates moving targets with light spots,which can not only control the motion trajectory of the moving target,but also achieve automatic tracking of its motion trajectory.This design takes the embedded chip STM32F103 as the core,processes image data through OpenMV,and adjusts the servo with precise PID algorithm to control the laser pen's spot to move and track on the screen according to the set program.After testing,the system can accurately complete the tracking and automatic tracking tasks of moving targets,with sensitive response and high cost-effectiveness.It can be widely used in intelligent control devices such as moving target tracking.

In order to enhance the convenience of smart home system and not destroy the structure of the original smart home system,new users and new terminal equipment can be added,a modular expansion system of smart home based on MQTT protocol is designed.The system uses MQTT protocol to manage gateway and users in a unified manner,and STM32F103RCT6 as a unified management terminal device for the gateway.At the same time,the cloud platform,WeChat mini program and gateway communication use the MQTT protocol to achieve remote transmission,and realize the function of the application side WeChat mini program for visual display and control management of home equipment status.The experiment results show that adding new users and new terminal equipment are simple,economical and efficient,and saves a lot of money for users.

Chiplet technology has garnered significant attention owing to its potential to enhance integrated chip yield,reduce research costs,and bolster efficiency.To facilitate the interconnection of distinct chips,high-speed data interfaces are imperative.With the aim of augmenting total bandwidth density,chiplet interconnections predominantly employ single-ended signals for data transmission,which are susceptible to common-mode noise,synchronous switching noise,and crosstalk noise.Chord signaling transforms single-ended signals into pseudo-differential signals through encoding and decoding transmitted data,enabling noise suppression and enhancement of signal transmission quality.Furthermore,as a modulation technique,chord signaling is extensively adopted due to its process independence,architectural flexibility,and strong process portability.This paper conducts a comprehensive review of prevalent chord signaling techniques,including analysis and summary of their performance.Finally,it offers a perspective on the chord signaling development.

In order to investigate single-event transient (SET) of 22 nm FDSOI technology, we have built a FDSOI NMOS model based on Sentaurus TCAD and carried out various SET simulations in 22nm FDSOI NMOS. The sensitive region, bias voltage and temperature dependence of SET in 22 nm FDSOI NMOS have been examined. The simulation results show that the sensitive regions in 22 nm FDSOI NMOS are the body region and LDD region near the body region. As the bias voltage increases, the total collected charge is increasing, and the width of drain transient pulse current is declining. Compared to the bias voltage, the effect of operating temperature on SET in 22 nm FDSOI NMOS is not significant.

Post-quantum cryptography has become a research hotspot in the current security field. In this paper, a secure SoC design scheme based on post-NIST quantum cryptography is proposed by studying Saber algorithm, which is a candidate of post-NIST quantum cryptography competition. The scheme firstly analyzes the hardware architecture of the algorithm, optimizes operations such as matrix operation and numerical splicing to improve hardware efficiency, and uses secondary verification to enhance the security of the decryption process of the algorithm, design Hash random number expansion generation module, encryption and decryption module and data storage and random number seed generator to complete the Saber algorithm hardware IP Core. On the basis of RISC-V processor, bus and interface circuit, a secure SoC based on post-quantum cryptography is designed with clock gating technology. The experimental results demonstrate that the area of the designed security SoC chip is 2.6 mm², with an equivalent logic gate count of 90k. The chip core area accounts for 75.2%, the PAD area accounts for 24.8%, and the chip power consumption is 9.467 mW.

Trusted execution technology for processors is a viable solution for protecting sensitive information,providing a secure and isolated environment for sensitive information processing to ensure information security and privacy protection.However,trusted execution technology for processors faces threats from various attacks.To systematically understand the research on vulnerability exploration in processor trusted execution technology,this paper first introduces trusted execution technologies such as SEV in AMD,SGX in Intel and TrustZone in ARM.Then,the methods of vulnerability research under different processor platforms are introduced.Finally,this paper discusses the potential applications of trusted execution technology in the field of industrial control system,and forecasts its role in ensuring the security of industrial control systems and points out directions for future research.

Neural Radiance Fields (NeRF) is an emerging method for reconstructing 3D scenes, garnering significant attention for its potential applications in the field of robotics. NeRF uses Multi-Layer Perceptrons (MLPs) to learn 3D scene features, achieving high-fidelity image rendering and providing a foundation for navigation, localization, and perception in complex environments. Its core processes, including ray sampling, feature extraction, and volumetric rendering, are computationally intensive and involve irregular memory access patterns, which limits deployment on existing hardware platforms, especially edge devices. To advance the practical application of NeRF technology, new hardware architectures and solutions for co-optimization of hardware and software are necessary. This review systematically elucidates the principles and evolution of NeRF technology, exploring the performance bottlenecks encountered during its hardware execution. The review provides a detailed review of classic NeRF hardware accelerators, summarizing three main optimization directions: image similarity optimization, spatial sparsity optimization, and memory access optimization, and analyzes the commonalities and differences among various techniques. Additionally, the review examines the technical limitations and challenges of current NeRF accelerators in handling open scene tasks, considering applications such as SLAM and AIGC, particularly in terms of scalability and storage constraints. Finally, the review offers suggestions for future development to inspire further applications and optimization of NeRF hardware accelerators.

Given the current usage status of natural gas flow computer software in China,there is an urgent need for a versatile and highly powerful flow computer system software.This article investigates the advantages and disadvantages of existing traffic computer system software in the market,and develops a universal traffic computer system software using programming software such as MySQL database and Visual Studio.At the same time,the practicality of the software is verified.The software adopts a menu framework structure,fully considering the requirements of on-site traffic computer operators.The system operation is simple and convenient,the functions are complete,and the page data is concise and easy to understand.

This paper designs and realizes a data communication interface between the host and ARM based on FPGA is designed and implemented.The PCIe interface function for interacting with the host and the FMC interface function for interacting with ARM are implemented by FPGA.The transmission performance testing of PCIe and FMC interfaces,as well as the data loop testing between the host and ARM had been completed.The test results show that the overall system design requirements have been achieved,with the PCIe 1.0 interface speed reaching 820 MB/s.

The evolution of electronic products towards miniaturization and intelligence is an inevitable development trend. High-density integrated circuit packaging technology is a key technology to achieve miniaturization of the product. In this paper, the packaging technology of high-density hybrid integrated circuit is studied. The packaging design of high-density hybrid integrated circuit is discussed from the aspects of substrate selection, structure design and heat dissipation design. On this basis, combined with the reliability requirements for non-hermetic hybrid integrated circuits, the article further studies the reliability evaluation method of high-density and non-hermetic hybrid integrated circuits. The effectiveness of the evaluation method is illustrated through practical examples. It can be used as a reference for the quality assurance system construction of domestic non-hermetic integrated circuits.

In order to evaluate the real-time clarity of video images,a new image clarity algorithm is designed and implemented on Xilinx A-7 FPGA chip.Firstly,a state machine design OTSU algorithm is used to calculate the adaptive threshold of the image to separate edges.Secondly,parallel processing and pipeline implementation are applied to improve the computational clarity of the 4-direction Tenengrad gradient function.The experiment results indicate that the design can complete 640×480@30 fps evaluation of the clarity of video stream images in 66 ms,with a certain degree of sensitivity.

Aiming at the requirement of high-speed and high linearity of CMOS image sensor for high-speed application devices,this paper realizes a Latch-ADC applied to image sensor on the basis of traditional SS ADC (Single-Slope ADC,Single-Slope analog-to-digital converter),with an operating frequency of 600 MHz.Latch-ADC can use multi-column pixels to share a Gray Code Counter,and quickly lock and store data through Latch structure,which realizes the functions of counter and SRAM in SS ADC.In this paper,a high-speed 12bit Latch-ADC is implemented by using 110 nm technology.Through simulation verification,the Latch-ADC in this paper has high linearity,with each conversion period of 7.094 μs,average power of 180.3 μW,and conversion power consumption of 1.279 nJ.

With the rapid development of the robotics industry, robotic technology has emerged as a new driving force for enhancing productivity, particularly highlighting the importance of technologies such as 3D reconstruction and obstacle avoidance navigation. However, active 3D imaging technologies based on Time of Flight (ToF) and structured light suffer from limitations such as low resolution, lack of original color information, and and susceptibility to ambient light interference, leading to suboptimal performance. Therefore, passive binocular stereo vision sensors, which can output dense depth and color information (RGB-D) in real-time, have been widely applied in fields such as autonomous robots, automobiles, and drones. Nonetheless, binocular stereo vision technology, which calculates disparity by mimicking human binocular vision for depth information, is computationally intensive and reliant on general-purpose computing platforms. This results in high energy consumption and latency for binocular stereo vision processors, limiting the technology's application in high-speed scenarios, small robots and edge computing. In recent years, binocular stereo vision processors integrated with hardware accelerators for stereo vision algorithms have gained significant attention in both academia and industry. This article systematically explains the theoretical foundation of binocular 3D stereo vision and its application examples in robotic stereo vision in the first section. It then introduces the structural components of binocular stereo vision processors, including core parts such as image acquisition, camera calibration and correction, and stereo matching. For the convenience of stereo vision hardware developers, this paper reviews the basic concepts, research status, challenges, and future trends based on the core components of the binocular stereo vision system, with a special focus on comparing new hardware computing architectures.

Aiming at the potential security issues arising from the existing deep learning edge applications relying on non-domestic FPGA architectures and encrypted IP implementations,which are difficult to quickly deploy on domestic FPGA platforms with insufficient IP and still under development,a neural network hardware deployment framework towards domestic FPGA is designed to achieve secure,autonomous and controllable deployment of domestic FPGA neural networks.In addition,the fast pipelined convolutional circuit and the im2col conversion circuit are designed to rapidly compute the systolic array.The experimental results demonstrate that the framework is capable of generating networks,such as Lenet5,with up to 147.8 GOPS for 16-bit data type and 0.024 ms running time,which represents a 5.13x improvement in throughput and a 6.67x decrease in time,respectively.An evaluation of im2col operation on RTL design yields up to 124.9x gains over CPU on Intel Xeon E-2276M.

In this study, a series of fan-out wafer-level packaging daisy chain test chips with various dimensions and specifications were fabricated. Temperature cycling tests were conducted on samples under different geometric parameters. Failure analysis of the failed samples was performed using techniques such as metallographic microscopy, scanning electron microscopy (SEM), and energy-dispersive X-ray spectroscopy (EDS). The failure modes of the redistribution layer interconnect structures in fan-out WLP were systematically investigated and summarized. This research provides guidance for reliability evaluation and high-reliability applications of fan-out WLP products.

FPGA chips have the advantages of high flexibility,fast speed and low cost,and have been widely used in all walks of life,especially in areas with high requirements for real-time and reliability of the system,such as aerospace and nuclear power DCS.The FPGA chip firmware is generally written through the special JTAG debugger,but the FPGA device cannot be updated and maintained by the special JTAG device after large-scale engineering application.In order to facilitate large-scale application and later maintenance,this paper proposes a method based on MCU simulation JTAG to realize the upgrade and update of FPGA.The subcontract sending response mechanism is designed to ensure the reliability of data download during the upgrade package download stage,and MCU simulation JTAG is designed to realize the upgrade and update of FPGA external Flash.The upgraded system will be used in the I/O equipment of NuCON nuclear DCS.It has great significance for the large-scale engineering application of equipment.

A set of intelligent monitoring equipment with low power consumption is designed for the intelligent monitoring of the environmental parameters in the missile storage and transportation box.Using ST's low-power chip STM8L152C8T6 as the processor and relying on MEMS sensors,the key parameters such as air pressure,temperature,humidity and shock in the missile storage and transportation packing box are monitored,and the production,service,transportation and other history information of the products in the box are recorded.Through various communication methods,real-time transmission of data and monitoring instructions is realized.At the same time,low power hardware and software design ideas are adopted to achieve ultra-low power operation of the equipment.The experiment results show that the intelligent monitoring equipment can realize the automatic real-time monitoring of the environmental parameters in the storage and transportation box under long-distance transportation and harsh storage conditions.The communication distance between the nodes of the regional LAN composed of intelligent monitoring equipment exceeds 200 m,and the single service life is greater than one year.

Aiming at the problems of increasing additional hardware overhead and sacrificing loading speed in the existing embedded OS loading mode selection method,an embedded OS loading mode selection method based on link state information is proposed.The method utilizes the reset of PHY and other peripherals after power-on and then reset the CPU,which runs the BootLoader to read and judge the link establishment signal of PHY to determine the loading mode,and if the link establishment signal indicates that the network has been connected,the Ethernet remote loading mode will be selected,while the local memory loading mode will be selected in all other cases.The results of engineering application show that the proposed method is stable and reliable.

To meet the high-precision and high-reliability requirements of aerospace products,and achieve self-reliance in components and chip localization,as well as application adaptability verification,it is necessary to design a domestic DC/DC board-level comprehensive testing platform based on FPGA.In long-term thermal environmental adaptability board-level verification projects,to achieve real-time monitoring of the working status of DC/DC device application boards,a smart recognition algorithm based on Transformer is proposed.The deep learning model is trained using these features.The experiment results show that for this 6-state dataset,the recognition accuracy of the Transformer model is 99.2%,which has good classification and monitoring performance and has certain engineering application value.

Aiming at the problems of low real-time monitoring performance and anomaly detection accuracy of power grid main equipment,a real-time monitoring system of power grid main equipment based on edge computing is constructed.The system collects real-time data of the state of power grid main equipment through the sensor module.Simultaneous Localization and Mapping (SLAM) is used to monitor the main equipment of power grid.The edge node module uses wavelet denoising to denoise the collected data,and uses the Local Outlier Factor (LOF) algorithm to detect the data outliers.The network node module uses Message Queuing Telemetry Transport (MQTT) to transmit the processed result value to the management platform.Through the analysis and display,alarm processing and permission setting of the management platform module,the real-time detection and early warning of the power grid main equipment status are realized.The experimental results show that the system uses LOF algorithm to detect outliers.The false positive rate is 1.5%,the detection rate is 98.5%,and the accuracy rate can reach 98.6%.The average time delay of data transmission using MQTT protocol is 31.52 ms, and the transmission rate can reach 99.78%,which is highly practical.

With the continuous iteration and development of computer vision technology, intelligent applications and devices centered on computer vision are increasingly playing a crucial role in daily life and work. Among these, visual Simultaneous Localization and Mapping (SLAM) technology finds extensive applications in fields such as robotics, drones, and autonomous driving. These fields critically rely on visual SLAM to provide accurate localization information for precise mapping and autonomous navigation. However, due to the inherent characteristics of visual SLAM algorithms, which involve high computational complexity and significant data dependency, traditional hardware platforms (CPU or GPU) struggle to meet the real-time and low-power requirements of edge applications. This limitation has become a key obstacle to the widespread adoption of visual SLAM. To address this issue, this paper proposes a high-efficiency domain-specific accelerator for ORB feature extraction in SLAM, designed through a co-optimization strategy of algorithms and hardware. Various hardware design techniques are employed to enhance computational performance and energy efficiency, include multi-level parallel computing based on decoupling data dependencies, data storage technology based on multi-size buckets, and pixel-level symmetric lightweight descriptor generation and direction calculation strategies. The proposed visual SLAM accelerator was tested and verified on the Xilinx ZCU104. Compared to the algorithm accuracy of ORB-SLAM2, the accuracy of this accelerator is within 5%, and the frame rate has increased to 108 fps. When compared to other hardware accelerators of the same period, the lookup table usage is reduced by 32.7%, the flip-flop (FF) usage is reduced by 41.17%, while the frame rate is increased by 1.4x and 0.74x.

This article uses agile development technology to design and improve the SM4 algorithm,and completes the implementation and verification on the Xilinx FPGA platform.In view of the shortcomings of the SM4 algorithm featuring long critical path and low throughput,a register group consisting of 32 registers is inserted into the round function calculation process as a cache area,and the pipeline method is used to shorten the critical path and optimize the S-box module structure,thus greatly improving the work efficiency.Frequency and throughput reach 340 MHz and 1.2 Gbit/s,respectively.At the same time,the new high-level hardware description language BSV is used for development,which greatly reduces the design complexity.Compared with the design using Verilog,the performance is 40% higher and the complexity is 60% lower without notable difference in hardware overhead.Compared with the earlier solution,the resource overhead is reduced by 70%,the performance is doubled,and it has higher application value.

Physical Unclonable Functions (PUFs) can be regarded as a "chip fingerprint" with lightweight, unpredictable, and difficult to clone characteristics, and have become an important component of IoT hardware security mechanisms. However, the implementation of traditional PUFs requires the addition of FPGA or dedicated integrated circuits at the hardware level, which will increase hardware costs. For billions of existing IoT embedded devices, it is difficult to increase PUF security attributes through hardware modifications. Therefore, we discuss the promising method to implement these intrinsic PUFs on commercial off-the-shelf devices and explore the potential applications of intrinsic PUFs. We will provide a systematic review of existing IPUFs, particularly Memroy based Intrinsic PUFs (MIPUFs), and discuss the feasibility and future development directions of IPUFs in existing systems, in order to promote the engineering application of this technology.

Image sensors,as crucial devices for capturing visual information,convert perceived light signals into electrical outputs.Currently,the manufacturing technology for image sensors based on complementary metal-oxide-semiconductor is quite mature.However,there is still a demand for miniaturized and multifunctional image sensors in certain specific application scenarios.Facing this challenge,image sensors based on two-dimensional (2D) semiconductors,with their rich material systems and excellent photoelectric properties,demonstrate potential in miniaturization and high integration,offering new opportunities for the development of the image sensor field.This paper first discusses the bandgap characteristics of 2D semiconductors and their corresponding spectral response ranges,showcasing single-pixel imaging technology based on 2D semiconductors.It then describes how the in-plane anisotropic properties of atomic arrangements in 2D semiconductors are utilized to successfully construct polarization-sensitive image sensors.Finally,it explores how the ongoing maturation of large-area growth technologies for 2D semiconductor materials can further facilitate the construction of image sensor arrays based on 2D semiconductors.

FreeRTOS is a free embedded real-time operating system,has the features of open source code,low configuration requirements,high efficiency,and overall function.The processors based on SPARC V8 architecture are widely used in aerospace fields such as satellite telemetry,remote control,attitude and orbit control,and autonomous management.The use of embedded operation system can improve the application range and reliability of satellite-borne applications based on SPARC V8 architecture,but there is no successful FreeRTOS porting case in China.The paper introduces the porting and debugging work of FreeRTOS on processor based on SPARC V8 architecture,combined with the characteristics of the window mechanism of SPARC V8 architecture.The test results indicate that the basic functions of FreeRTOS are operating normally,it can be used for development of the satellite-borne application on SPARC V8 architecture.

This paper evaluates the thermal reliability of assembly process of Fan-out Wafer Level Package based on simulation. Firstly, we briefly introduce the critical technologies of Fan-out wafer level package and analyze the possible failure mechanism of these advanced packaging technologies. Then, for a typical package structure based on Fan-out wafer level package technology, the 1/4 structure finite element model is established. The simulation of the critical structure under the typical military thermal cycling condition is conducted. By analyzing the stress and displacement of the key structures of the package, potential reliability vulnerabilities leading to failure of fan-out wafer-level packaging have been identified.

Electromagnetic fault injection (EMFI) has become an effective fault injection attack technique threatening integrated circuit (IC) security.Existing research has demonstrated that EMFI perturbs circuits' internal states by inducing parasitic current on the IC power grid.Finite element analysis of the power grid under EMFI shows that the induced current could increase the IR drop of the power grid,leading to circuit faults.Therefore,to address this problem,we propose a power supply port placement optimization approach which reduces the effect of the induced current.The experiment results show that by optimizing the positions of the power supply ports,the worst IR drop can be reduced by 40%,enhancing the robustness of the power grid.

Bluetooth Mesh networks use flooding for multi-hop communication.Without the routing mechanism,the original flooding mechanism will increase the network overhead and communication delay due to the continuous broadcast of messages.In this paper,based on the improved energy efficient AODV algorithm E-AODV,MATLAB is used for simulation,and the optimal node is selected for packet forwarding according to hop count,node residual energy and link quality.The simulation results show that the E-AODV algorithm can reduce the number of RREQ packet transmission in Bluetooth Mesh network.Compared with traditional flooding and AODV algorithms,the algorithm can effectively reduce packet transmission delay,reduce network energy consumption,and improve network performance.

In the development and design process of integrated circuit manufacturing,especially semiconductor memory,the use of efuse is often involved,which is applied in various scenarios,such as chip protection,circuit calibration and so on.In the paper,a custom efuse communication protocol is proposed and a verification platform based on UVM is built to verify its functions.The validation results show that the requirement functionality can be achieved with this protocol and has good robustness.

The parameter performance of each load on the probe in the process of space exploration has great significance to the performance evaluation and structural optimization of the probe.In order to solve this problem,this paper designs a multi-channel,high-speed data acquisition and storage device with field programmable gate array (FPGA) as the core by using a high-performance A/D conversion chip to realize real-time acquisition,conversion,framing and data storage of 16 analog signals,as well as the reception of LVDS transmission data.Then it is transmitted to the system process control unit in real time through the GPIO bus,and can also be stored in Flash memory to realize communication and external telemetry with the host computer through Gigabit Ethernet.The experiment results show that after data comparison,the collected data is consistent with the data source,there is no frame loss and no error code,and the data acquisition and storage meet the technical requirements and realize the expected function.

In the face of the problems of hardware development constraining software development, hardware resource constraints, and insufficient testing in the application of embedded development boards in the aerospace field, virtualization solutions are introduced for the hardware platform on which a certain type of flight control software depends. Firstly, an AArch64 instruction test set was written to verify the credibility of QEMU dynamic translation, and Flash was successfully mounted by debugging, tracing, changing, and compiling the QEMU source code. Secondly, a new equipment simulator was created, the network communication mode of the model machine was adjusted, and the virtual machine, simulator and model machine were jointly debugged to ensure the normal data transmission, so as to smoothly build a virtual platform. Furthermore, an integrated development environment is designed to support functions such as the visual construction of the virtual platform, remote debugging of source code, target code coverage statistics and to improve the convenience and reliability of the virtual platform. Finally, it is observed that the simulation results of a certain type of flight control software are consistent on both the real platform and the virtual platform, verifying that the virtual platform is real and usable.

In Visual Simultaneous Localization and Mapping (V-SLAM) systems, Bundle Adjustment (BA) plays a crucial role in optimizing camera parameters and the positions of 3D points. However, due to the high computational complexity and real-time requirements of BA, traditional computing platforms struggle to meet efficiency demands. Recently, the introduction of dedicated hardware accelerators has provided new solutions for BA optimization. This paper reviews the current status of research and development trends in BA optimization-specific chips. It covers the application scenarios, definitions, and basic principles of BA algorithms; the acceleration of BA on Field-Programmable Gate Arrays (FPGA), Application-Specific Integrated Circuits (ASIC), and Graphics Processing Units (GPU), as well as the development trends of these accelerators. Furthermore, this paper discusses the technical challenges in implementing BA accelerators and anticipates future development directions. By summarizing current research advancements, this review aims to provide guidance and insights for future studies on BA optimization-specific chips.

Radio frequency identification technology has been widely applied in fields such as logistics and inventory management,but there are still problems such as low positioning accuracy and poor stability in indoor positioning applications.In order to improve the accuracy and stability of positioning,the extended Kalman Filter algorithm,unscented Kalman Filter algorithm and UKF-RTS algorithm combining UKF and Rauch Tung Streebel (RTS) are used in the study.In order to optimize the accuracy of RFID positioning,the EKF,UKF and UKF-RTS algorithms are introduced.The maximum error of the UKF method is about 0.42 m.However,the maximum accuracy of UKF-RTS can be reduced to around 0.26 m.The UKF-RTS algorithm has the smallest error and improves positioning accuracy by 48% compared to the EKF algorithm and 25% compared to the UKF algorithm.Especially when dealing with changes in motion status,UKF-RTS performs well and is expected to provide new research directions for the development of RFID indoor positioning technology.

The use of epoxy adhesive die attach material in integrated circuits is gaining popularity. Die attach epoxy adhesive resin bleed is commonly observed during the curing process. A reliability issue for wirebonding will occur if the material spreads over an area where wirebonding is to be performed. In this paper, an approach involving contact angle measurement is used to determine the mechanism of resin bleed. In addition, the effect of roughness of the substrate on resin bleed is also discussed. Priliminary results suggest that vacuum baking plays a significant role in resin bleed while no correlation was seen with roughness of substrate.

Despite the intense attention to badminton, there are relatively few intelligent devices specifically designed for this sport. Therefore, this study verifies algorithms based on traditional shallow machine learning models such as Random Forest (RF), K-Nearest Neighbor (K-NN), Gradient Boosting (GB), Support Vector Machine (SVM), and Long Short-Term Memory (LSTM) deep learning models to accurately identify five common badminton swing actions: overhead forehand stroke, aerial backhand stroke, smash, underarm forehand strokes, and underarm backhand stroke. This study collected 1 800 sets of swing motion data samples from 12 athletes using a wireless inertial sensor module fixed at the bottom of the badminton racket grip. Low power Bluetooth was used for data transmission and collection. The real-time data collected was intercepted using a window cutting method that combines action window and sliding window. The feature of the intercepted action data was extracted. RF, K-NN, GB, SVM, and LSTM models were used to learn and verify the recognition of five swing movements during the experiment. The experimental results showed that LSTM reached a recognition accuracy of 99.42%, significantly outperforming traditional machine learning algorithms. Additionally, this paper selects STM32F476 ARM microcontroller as the edge computing unit, and deploys the badminton swing action recognition model into it. This deployment enables real-time inference and recognition of badminton swing types by athletes, demonstrating effective recognition performance.

In Internet of Things (IoT) systems,Resistance-Capacitance (RC) relaxation oscillator has been implemented to reduce power consumption.To address the issue that uncompensated traditional RC oscillators are susceptible to power supply and temperature influences,the Forward Body Biasing (FBB) technique is employed to reduce the temperature drift of the low supply voltage digital buffer.Additionally,leverage Subthreshold Leakage Current (SLC) compensation and Subthreshold Leakage Suppression (SLS) in high-temperature subthreshold MOS transistors are used.Compared to uncompensated oscillators,the temperature stability is enhanced by 38 times.A relaxation oscillator based on 65 nm CMOS is designed.With a power supply voltage of 0.4 V at room temperature,the power consumption is 8.1 nW,operating at a frequency of 4.4 kHz.The energy efficiency is calculated at 1.84 nW/kHz.Within the range of -30℃ to 90℃,the temperature stability of the oscillator is measured at 75.1 ppm/℃.

In the detection of shallow underground explosion-induced vibrations,the test environment noise is large,and the signal frequency of the explosion-induced seismic waves is relatively high.However,conventional seismic detection instruments have larger background noise and lower sampling rates,making it difficult to meet the needs of explosion-induced vibration detection.Therefore,a vibration detection system is designed based on ZYNQ.Firstly,a high-precision sensor ADXL354B is used to acquire explosion-induced vibration signals.A conditioning circuit is designed to filter out high-frequency noise and improve the signal acquisition accuracy.At the same time,a high-precision and high-sampling rate 24 bit analog-to-digital converter AD7768 is used for data conversion.Then,the logic design is carried out in the PL part of the ZYNQ chip,and the PS part uses the driving separation method to customize a Linux system for data processing and transmission.Finally,a semi-physical simulation platform is built to functionally verify the vibration detection node.The experimental results show that the system is superior to domestic similar seismic exploration instruments in terms of sampling rate and system noise.It can synchronously collect acceleration signals at a maximum of 256 ksps,24 bits,and 8 channels and transmit them in real-time to the host computer.This result has strong application value in the field of shallow underground vibration detection.

Terahertz wave is an electromagnetic wave between millimeter wave and infrared light,which has many feature like strong penetration capability,non-ionization and high instantaneous bandwidth.For these qualities,terahertz waves have a wide range of potential applications in non-destructive testing,medical imaging,safety inspection,and other areas.In the imaging system,the detector is an essential part.This paper presents a structure that combines the output of narrow-band detectors with different center frequencies to realize wide-band detection.In order to reduce the area,these narrowband detectors adopt a nested structure,which means that the high-frequency narrowband detectors are placed inside the low-frequency narrowband detectors in turn.Each narrow-band detector includes a loop antenna,a matching network and a field effect transistor (FET) detector circuit.The detector is fabricated in a 65 nm standard CMOS process,and the detection frequency range covers 100 GHz to 1 000 GHz.Based on this broadband detector,we propose a terahertz focal plane imaging system,which mainly consists of a terahertz radiation source,a PTFE lens,a broadband CMOS detector,etc.The measurement results have shown that the focal plane imaging system is capable of stably imaging at frequencies of 100 GHz,220 GHz and 300 GHz.The imaging quality improves significantly with increasing frequency.In order to solve the problem of missing information in measurement images,the morphological closing algorithm is used to process the original image.This algorithm effectively fills in the missing information and enhances the quality of the image.

Substrate integrated waveguide (SIW) filter power dividers (FPDs) are widely used in communication systems.Similar to traditional waveguide resonators,SIW resonators contain numerous transmission modes,which makes the wide stopband characteristics of SIW FPDs difficult to achieve.In this paper,a substrate integrated waveguide filter power divider with ultra-wide resistance implemented by electric excitation is designed.Specifically,a forth-order substrate integrated waveguide filter power divider based on electromagnetic alternating coupling topology with electrical input and electrical output ports is proposed.The lateral coupling is achieved by opening a window on the side of the resonator to achieve magnetic coupling,and the longitudinal coupling is achieved by etching an S-slot line in the coupling window between two adjacent cavities.Multiple higher-order modes can be suppressed through the orthogonal transmission path,so that the simulation and measurement results show that the out-of-band suppression effect of the filter power divider with a center frequency of 35.5 GHz is better than -20 dB respectively in the stopband bandwidths greater than 9f₀ and 3.1f₀.The experimental results are in good agreement with the simulation results.

To reduce data route and communication links and improve the real-time reporting of pre-warning event data and the timeliness of event detection,video event detection and recognition are directly connected and integrated with real-time Ethernet communication at the edge control end.The developed slave station controller packages the identified data,similarity scores,and real-time collected digital and analog data to the monitoring master station,and the master station communicates with the slave station through preset control logic to realize remote control and management of objects.Additionally,ultra-long-distance communication is realized through the cascade networking of SFP optical module communication mode,which reduces the complexity and cost of on-site wiring.

Based on the existing ZYNQ+FPGA ADC universal testing platform of the 58th China Electronics Technology Group Corporation,this paper carries out a detailed dynamic index test for the six-channel analog-to-digital conversion device AD73360.Data processing and analysis are realized by invoking MATLAB in LabVIEW of upper computer.As a result of the acquisition control and processing system has been designed,the design is mainly for AD73360 slave card's hardware design,concrete dynamic testing methods and PC by detailed test.Through comparing the manual gives typical dynamic index,the slave card performance can satisfy the performance index of AD73360.

Aiming at the challenges of intricate computational requirements and a sluggish detection pace,and poor robustness of traditional algorithms for detecting and tracking moving objects,a proposed approach aims to attain efficient moving object detection and tracking by dynamically adjusting the detection area.Utilizing an enhanced inter-frame difference algorithm for the extraction of moving targets,the information regarding the size and location of the target are transmitted to the region cropping algorithm and the Kalman filter tracking algorithm,respectively,to achieve reduced detection range and target tracking.Using an improved method for a resolution of 640× 480 images are used for experiments,and a target size of 66 is detected to 64×84,the adjusted detection area size is 132 ×168,the computation of the inter frame differential detection part is reduced by 92.78%,and the tracking effect based on the target position is better,this approach has been confirmed to be correct in FPGA.

Aiming at the problem that part of the interface of the missile post-flight data recording device is damaged and the flight data cannot be read back smoothly.A Flash read-write device that can read back the data in the memory chip at a high speed is developed,and a high-speed parallel transceiver link with a rate of 1.562 5 Gb/s per channel is designed by using Aurora protocol on the basis of the built-in LVDS transceiver in FPGA,and an alternate serial readout link with a low transmission rate is designed on the basis of serial parallel conversion.Both the high-speed reading interface and the standby reading interface can transmit the data in the Flash chip to the test table for evaluation and utilization without losing frames.It has the features of simple hardware design,convenient and fast reading back data.

Aiming at the shortcomings of all digital phase-locked loop (ADPLL) in terms of frequency hopping time,signal quality,frequency stepping,the loop structure and digital phase-locked algorithm of ADPLL are optimized,and a new type of all digital phase-locked loop structure is designed.This structure adopts a Fast Frequency to Voltage Converter (FVC) to replace the digital frequency and phase discriminator and digital filter in ADPLL.FVC calculates the output frequency value directly by doubling the reference frequency and counting the feedback frequency,thereby determining the error between the output frequency and the target output frequency.By establishing a functional relationship between frequency error and voltage adjustment,FVC controls the fast locking of the output frequency,achieving small frequency steps and high-quality fast synthesis frequency output.Finally,the feasibility of the new all digital phase-locked loop structure has been verified through simulation and actual measurement.The actual test results show that the frequency near end spurious synthesized by this technology is -87 dBc,the minimum frequency step can reach 191 Hz,and the minimum frequency hopping time is 3.9 μs.

Reconfigurable computing technology solves the contradiction between computing performance,efficiency and flexibility very well.As a very important part of heterogeneous multi-core platform,DSP has few researches on its reconfiguration,which limits the application of this technology.To solve this problem,a global dynamic reconfiguration method based on DSP is proposed.Pre-partition FLASH memory and burn SPI parameter files as well as image files A and B.After the system starts,it runs image A first.When receiving the reconstruction command,modify SPI parameters to point the image in BOOT to B.Finally,control the DSP to restart BOOT to complete the reconstruction.The test results of TI TMS320C6678 DSP show that this method can complete the switching of DSP running image within 320 ms,and has a good application prospect.

The reliability characterization of industrial-chip-featured MOS devices typically involves accelerated life tests based on constant voltage stress or voltage ramp stress methods, followed by lifetime evaluation based on the test results. As test conditions for these methods are relatively simple, they fail to satisfy the requirements of the common electromagnetic interference environments faced by industrial chips. The degradation of MOS devices in real scenarios is challenging to effectively delineate, thereby affecting the precise assessment of the operation state of chips. In this research, we propose a MOS device life assessment method from a micro perspective, combined with TCAD simulation software, to predict the life of MOS devices under electromagnetic interference environments. The method effectively avoids the error feedback caused by fluctuations on device outputs. The device life predicted here is somewhat conservative, which, to a greater extent, ensures the stable operation of chips in electromagnetic environments.

In order to improve the accuracy and speed of missing insulator identification, an automatic insulator defect detection system based on UAV inspection images and Dandelion Algorithm (DA) is designed. UAV detection technology is used to locate and detect missing insulators of power transmission lines. Then, feature extraction is carried out on the automatic identification image of insulators obtained by UAV, and the operation and inspection path of UAV are planned. The feature vector of missing insulators of power lines is calculated. The feature image of missing insulators of power lines is processed by fitting the least square method. Obtain the location of the missing insulator to achieve accurate location of the defect. In this process, a Dandelion Algorithm is introduced to optimize the PID control parameters of UAVs. The seeding behavior and mathematical model of dandelion are described in principle, and the parameters are optimized by this algorithm. The test results show that the accuracy rate of target recognition is up to 98%, indicating that the research system is highly practical.

The traditional switched-capacitor (SC) capacitance-to-digital converter (CDC) based on SAR ADC uses high-voltage power supply to increase output swing in order to achieve a high capacitance detection range. However, to maintain noise performance, they require high current drive, significantly increasing system power consumption. To address the above issues, this article proposes a capacitance-to-digital converter based on a digital amplifier, which uses the CDAC array as the analog output to bear high voltage. Only the CDAC array and sensing capacitors are driven by high voltage (5 V), while the rest is still powered by low voltage (1 V), allowing the CDC to achieve high dynamic range and sensitivity while maintaining low power consumption and low noise. In addition, for the optimization of noise, this work achieves first-order noise shaping for SAR ADC by adding an integral loop in the digital amplifier, reducing the quantization noise of the system and improving the effective number of bits for CDC. On the other hand, by introducing active noise cancellation (ANC) technology, the system's aliasing noise is reduced and the signal-to-noise ratio is improved.

A surface-potential-based I-V model for junctionless gate-all-around transistors is presented in this paper. Based on the one-dimensional poisson equation, combined with the corresponding boundary conditions, the nonlinear system of transcendental equations based on physical principles in two analytical models is sequentially solved using the Runge-Kutta algorithm, establishing the numerical models of the surface potential, midpoint potential, and gate pressure. Subsequently, Pao-Sah integration is used to derive the drain current of gate-all-around field effect transistors through the results of the surface potential expressed in form of the intermediate parameter. The proposed physics-based I-V model results exhibit good agreements with numerical and experimental data, validating the feasibility of the modeling approach for gate-all-around field effect transistors. Moreover, this method realizes the combination of analytical and numerical models and achieves a good balance between accuracy and efficiency.

With the widespread application of artificial intelligence technology,low-cost solutions in the field of instrument reading recognition have gradually been applied.At present,there are water meter reading heads based on NB technology for image recognition on the market,but they rely on the operator's NB network coverage and signal quality.Only large cities and major urban areas in counties have good coverage,and there is little network coverage in suburban and rural areas.In the paper,a low-cost terminal is designed based on the STM32WLE5 chip to collect dashboard photos.Through LoRa technology,the image information is transmitted back to the user service platform for AI recognition and reading.This system can solve the problem of NB network not covering regions,and has complementary or even substitutive effects in the market.The experimental results show that LoRa image transmission is stable and reliable,meeting the quality requirements of image recognition.

An adaptive neuro-fuzzy inference system (ANFIS)-based method for correcting outliers in power demand curves is proposed for outliers in smart grid big data. The method performs big data analysis for smart meters in smart grids to detect and correct zero-value anomalies in timing data. The effectiveness of the proposed method is verified using real power demand data, and the results show that the ANFIS method is able to correct the outliers with higher accuracy compared with the linear interpolation and artificial neural network based methods, with a maximum relative error of only 3.76%. In addition, the standard deviation of the relative error is also smaller at 2.26%. The experiment results show that the ANFIS method fully combines the advantages of fuzzy logic system and neural network, effectively dealing with the outliers in the peak hour power load demand curve well. This provides a valuable reference for further improving the effect of smart grid big data analysis.

To address the problems challenges such as high flight altitude, large changes in target scale, and the densely occluded targets, the study utilizes deep learning methods for target detection and identification and visual localization of UAV. A UAV target detection and positioning system is designed and discussed in depth. The study selects Yolov5 deep learning network model for target detection, completes end-to-end training prediction based on Darknet deep learning framework, and finally utilizes AprilTag visual benchmark library to complete the auxiliary localization of UAV's spatial positioning. The test results show that the parameter count of Yolov5 model is only 5.3. Meanwhile, the model achieves a precision of 97.41%, a recall rate of 90.73%, and an mAP of 83.2. The fitting precision of AprilTag assisted localization is more than 95%. The research and design of intelligent UAV vision system based on deep learning not only has actual engineering values, but also significant societal importance.

Direct Memory Access (DMA) is a high-speed and high-efficiency transmission method for a large amount of data transmission between various modules.After the CPU initializes and configures the DMA,the DMA is allowed to occupy the bus as the host,and can directly read and write the data of the peripheral devices and the memory,so as to realize the data transfer between the peripheral devices and the memory,and between the memory and the memory,without the intervention of the CPU.The design liberates the CPU and greatly improves the efficiency of data transmission.This paper aims to realize data transfer between peripherals and memory of the dual-channel DMA controller based on the AHB bus protocol.

In current aerospace missions,the SRAM-based FPGA is susceptible to single-event effects,resulting in unexpected functional failures.In order to mitigate the impact of single-event effects and reduce the workload of repetitive design and testing,a bus-based FPGA program upload-scrubbing ASIC is designed.The ASIC supports multiple buses,adapts to various FPGAs,and is compatible with different memory types.It is utilized for tasks such as FPGA program loading,scrubbing,program upload,and other on-orbit maintenance operations.Firstly,the ASIC's system-level design,module-level design,and workflow planning are presented.The principle of ASIC resistance to single-event effects is briefly described.By designing compatible communication protocols,the ASIC simultaneously supports CAN bus and RS485 bus.By analyzing the FPGA configuration bitstream structure,the ASIC supports loading and scrubbing 9 types of FPGAs and achieves domestic compatibility.By converting the data format of memory,the ASIC can store the configuration bitstream in various memories,including BPI Flash,SPI Flash,PROM,and others.The triggering of scrubbing,SEFI detection,and execution of scrubbing are discussed.Analyzing and simulating the factors affecting the upload speed of the ASIC.Utilize prototype verification board,ASIC verification board,and pluggable FPGAs and memory floating small boards to complete various functional verifications before and after tape-out.The verification results are as expected.The effectiveness of the scrubbing is evaluated and compared with other on-orbit maintenance schemes.The bus-based program upload-scrubbing ASIC has certain advantages and can efficiently and reliably meet the various on-orbit maintenance requirements of aerospace FPGA.

In view of the difficulty in collecting panoramic information of power grid transmission lines and the inaccuracy of point cloud information processing,a three-dimensional airborne radar point cloud information acquisition system for power grid panoramic transmission lines is proposed.The system realizes the design and selection of airborne radar hardware through the design of airborne radar signal processing system and the selection of acquisition equipment.It uses LiDAR combined with Inertial Measurement Unit to accurately collect point cloud data of transmission lines.Using the combination of color information and intensity information in point cloud data,the point cloud data is classified and processed to realize the processing of point cloud data information.The experiment results show that the acquisition error of the system is smaller than that of LiDAR only,and the maximum error is 0.21,and the minimum error is 0.08.The classification accuracy of the system for different objects is different,and the classification accuracy of the transmission line can reach 97%,which is higher than the traditional method and the single point cloud data processing and classification method based on intensity information.

In order to solve the problem of data transmission failure caused by external factors affecting data channels under special conditions,a dual backup data transmission design scheme based on SRIO is proposed.In the design,two independent SRIO IP cores are used to achieve independent transmission of data from the main channel and backup channel,and backup selection of data transmission channels is carried out through the channel selection module.This solution uses Xilinx's Kintex 7 series FPGA as the connection device for SRIO,and the physical layer uses the GTX high-speed serial transceiver integrated inside the FPGA chip as the transmission foundation.The transmission link uses "Optical module+optical cable" instead of cable to realize high-speed and reliable data transmission.This scheme has been applied to the telemetry system data acquisition device project to achieve dual backup data transmission between FPGA devices.

With the gradual replacement of traditional energy by new energy, and the development of the state grid smart grid, it is possible to connect new energy generation to the grid. In the new power system, the high proportion of new energy access has strong uncertainty, large fluctuation, and serious distortion of current waveform, which will impact the traditional electric energy metering equipment, resulting in a large measurement error when the original electric energy metering equipment is used. In order to meet the requirements of the new power system measurement, the paper is based on zero flux current sensing technology, non-pole smooth amplification technique, high-precision angular difference compensation method to achieve accurate measurement of energy meters under wide dynamic and multi feature parameters. The experimental results indicate that the new energy metering scheme can be applied to wide dynamic range, low power factor, and bidirectional power flow conditions under new energy access, effectively improving the overall efficiency of the power system. The research results of this paper provide important guidance for the optimization design of various energy metering technologies and algorithms as well as for applications of energy metering in the field of new energy.

By introducing resistance into the equivalent circuit model of power VDMOS devices, the influence of device surface voltage on its Single-Event Effects (SEE) is analyzed. Based on simulation data, the influence of parameters such as neck width, P+ implants, and reverse transfer capacitance (Crr) on the device is analyzed. A 250 V device is designed and tested under irradiation conditions. The simulation and experimental results are consistent with the conclusions of the model analysis. Under irradiation conditions, the surface voltage is determined by the partial voltage of the resistance. Increasing the injection dose of P+ implantation and reducing the width of the neck region can reduce the resistance and improve the device's ability to resist single particle effects. Conversely, reducing the neck concentration to form a low Crr has no alleviating effect on the SEE. In addition, devices with increased neck width show increased leakage after irradiation.

The effective mining of dialogue information of infrastructure projects is an inevitable trend in the development of infrastructure field, and also a necessary means to achieve high-quality development of infrastructure projects. Based on knowledge graph and big data, the algorithm of dialogue information mining in infrastructure field is studied. Corresponding to the entire process of infrastructure project construction with the theory of full lifecycle, we design a dialogue information database for infrastructure projects based on demand analysis, and define a dialogue information data flow graph for database application logic. Through the presentation form of the data flow map, select the knowledge graph algorithm to mark the dialogue information type label, and determine the specific relationship of the dialog information in the infrastructure field in an extensible mode. In order to ensure the determined relationships of dialogue information are correlated, the similarity between the corresponding information relationships is calculated through the similarity evaluation method in big data technology. The data correlation probability is calculated by combining the similarity, to realize the dialog information mining in the global domain and complete the algorithm design. The experimental results show that the new algorithm can achieve precise mining of different information elements by mining and validating different types of dialogue information in infrastructure engineering, demonstrating practical value.

In the paper,a high-precision time-keeping technology is proposed for the time-keeping characteristics of rubidium atomic clock.It uses intelligent temperature and frequency drift separation algorithms to automatically separate temperature and frequency drift characteristics,and uses multiple curve fitting methods to fit frequency drift and temperature characteristic curves separately.During the time-keeping process,accurate compensation is carried out separately,thus to achieve high-precision time-keeping of rubidium atomic clock.

There are risks of malicious attacks on SoC chips with JTAG/cJTAG interfaces that are not disabled during the mass productization stage, or the JTAG/cJTAG interfaces are simply and permanently disabled by OTP/eFuse, which makes it difficult to locate problems during mass production or limits debugging means when the CPU pointer runs away, making it difficult to locate the problem. This article designs a SoC security chip debug system based on permission management. Compared to traditional debugging methods, this article has made two modifications. For JTAG/cJTAG debugging, permission control bit design, verification password design, and permission comparison design have been added while retaining traditional debugging methods. Regarding the UART debugging method, a UART access register bus design has been added on the basis of retaining traditional debugging methods, and the UART access register function can be disabled through OTP/eFuse. It not only provides problem analysis methods for SoC chip CPU hanging and pointer running away, but also provides secure and convenient JTAG/cJTAG/UART debugging for SoC chip mass production stage.

To solve the problems of traditional ADS-B signal decoding system,including low decoding accuracy,low data transmission rate and poor real-time decoding,this paper proposes a solution based on AD9361 and Xilinx's Zynq-7000 universal software radio platform.The scheme improves the decoding accuracy by improving the ADS-B signal sampling rate,and the principle is explained and verified.In addition,in order to deal with the problem of increasing data volume due to increasing sample rate,we introduce the chain storage structure as the cache area of DMA.The experiment results show that compared with the traditional decoding system,the proposed system can recognize and decode ADS-B signals with 10% higher accuracy.The introduction of chain storage structure improves the data processing speed and meets the demand of aircraft track real-time display.In addition,the data transmission rate of the system can reach up to 682 Mb/s to meet the needs of high-speed data transmission.

This paper presents a high-efficiency wide input voltage boundary conduction mode flyback converter.To prevent chip overshoot and undervoltage during load switching,a new mode switching loop composed of current regulating circuit (CRC) and adaptive frequency control circuit (AFCC) is proposed.This configuration facilitates smooth transition between different modes,enhancing the transient response of load and the conversion efficiency of chip.Additionally,the current regulation control technology is introduced into the loop to reduce the charge current on the primary side in low ripple burst mode which lowers the minimum load current on the secondary side,thereby reducing switching frequency under light loads and power consumption.Based on the 0.18 μm BCD process,the circuit design and layout design are realized,and the chip area is 1.48×2.5 mm².The simulation results show that under input voltage ranging from 3~32 V and output voltageat 5 V, the maximum change of the transient response of the output voltage is 6% and the peak conversion efficiency reaches 88.6%.

Based on the long-term stability of navigation satellite timing,combined with the excellent short-term stability and low drift rate of rubidium atomic clock,a high-precision timing technology is proposed.It tames the rubidium atomic clock based on 1 PPS of navigation receiver to provide high-precision timing service through three key technologies:precise clock difference measurement,Kalman filtering,and incremental PID algorithm.The verification results show that the phase stability of the output 1 PPS reaches within ±0.2 ns,the stability reaches 3.76E^-12 at 1 s during taming.

Aiming at the problem that the positioning accuracy of common integrated navigation systems will decline rapidly in areas with weak satellite signals such as tunnels,canyons,forests,etc.,a Beidou/strapdown inertial navigation (SINS)/odometer (OD) integrated navigation and positioning terminal is designed.The terminal design takes OMAP-L137 processor as the core,including Beidou,SINS,odometer,4G communication and power supply modules.The data processing part takes the difference between the Beidou navigation receiver and the pseudo range and pseudo range rate calculated according to SINS/OD as the measured value,and uses the extended Kalman filter (EKF) algorithm for data fusion and error estimation.The experiment results show that the maximum position error of Beidou/SINS/OD integrated navigation and positioning terminal is 46.82 m and the error drift is 0.94% when the total mileage is 5 km when the satellite is unlocked,which can effectively improve the problem of positioning accuracy decline caused by the obscuration of satellite signals,smooth the vehicle trajectory and improve the navigation and positioning accuracy.

In the traditional remote measurement technology based on the Internet of Things,there are many problems such as the measurement accuracy and sensor cost cannot be balanced,the real-time data update is not good,and the communication cost is too high.Based on this problem,a data acquisition scheme is proposed,which uses software algorithms to achieve high precision.At the same time,LTE-Cat-1 is used as the data communication method to transmit data to remote cloud servers and terminals.The program is applied to the remote altitude measurement.After rigorous calculation and test verification,the absolute error of the measurement is less than 5 meters,the relative error is less than 0.5%,the stability of data transmission is high,and the real-time transmission can be controlled to less than 1 second.Internally,the cost of communication is taken into account at the same time.When the data upload frequency reaches 1 time/s,the data flow can be controlled at 600 KB/h,which meets the requirements of high precision,low cost,high real-time performance and stability of the system.

In view of the high encryption requirements of relevant IoT platforms in China,but the development of encryption technology is slow,a password security authentication system based on hybrid encryption in IoT is designed in the paper.In order to ensure the security authentication of users entering the network,this study adopts the elliptic curve cryptography for the first time.The hybrid encryption technology of ECC and AES realizes the design and implementation of the password security authentication system.By using the characteristics of ECC algorithm elliptic curve,it can use the key more convenient than the general encryption technology and obtain the same security.Further,the extended process of AES algorithm is improved to improve the security of the algorithm,and the column obfuscation operation is optimized to improve the running speed of the algorithm.Finally,combining the advantages of the two algorithms,a hybrid encryption system is constructed which is convenient for key management and can take into account both efficiency and security.Finally,a hybrid encryption system that is convenient for key management and can take into account both efficiency and security is achieved.Through the experiment,the system technical accounting data,error rate in the acceptable range,the study lays a foundation for other technical research.

In response to the increasing demand for insulation testing in the industrial field,a wide range insulation testing system based on FPGA is proposed.At the same time,in response to the impact of power frequency interference on testing accuracy in high resistance testing,a method using dual T-notch filters is proposed.Firstly,analyze the testing principle of the insulation testing platform and provide the overall design framework of the system.The insulation testing platform is divided into two parts:the upper computer and the lower computer,which communicate through Ethernet.Secondly,analyze the circuit principle and propose corresponding hardware design based on the principle and testing requirements.The notch filter adopts a dual T structure,and the resistance testing principle adopts a two wire method,design software and communication protocols based on circuit and testing principles.Finally,the circuit is simulated and tested in physical form.The test results show that the insulation testing system can cover a testing range of 10 Ω~10 MΩ,and the dual T notch filter can filter out power frequency interference in the case of high resistance testing.The test errors after filtering are all within 10%.

The inherent capacitor mismatch resulting from process variations is a significant impediment in the designing of high-resolution Analog-to-Digital Converters. Various calibration methods have been previously introduced, often employing additional circuits or external controllers, albeit at the expense of increased silicon area or intricate operational complexities. In this work, we have established the relationship between capacitor mismatches, output deviation, and Total Harmonic Distortion in capacitor Digital-to-Analog Converters. Consequently, the statistical distribution of expected THD under certain mismatch can be derived. After that, we propose a new compensation strategy that adopts the Dynamic Element Matching technique to conventional cyclic ADCs with minimum hardware cost and implement this compensation scheme in a cyclic-pipelined ADC. We reassess the performance of the proposed ADC based on the formulated theory. Importantly, the measurement results of the cyclic ADC have not only confirmed the validity of our proposed theory but also demonstrated the robust performance of the simplified version of the DEM algorithm. This work is constructive for performance estimation in other high-precision ADC designs.

The existing radio frequency fingerprinting technique lacks theoretical support and cannot get rid of the suspicion of identifying the process of device identification with the help of channel features.In this paper,a radio frequency fingerprint extraction method based on spread spectrum reduction is proposed for ZigBee signals with direct sequence spread spectrum.The method achieves device classification accuracy up to 99.8% on 60 ZigBee devices and in four different experimental scenarios.The method is more robust and less computationally intensive,making it highly practical.

This paper presents a design scheme for an efficient instrument management system centered on the ATMEL(acpuired by Microchip) 32-bit SPARC V8 architecture processor AT697, with interface expansion facilitated by FPGA. The design optimizes the monitoring and control management of complex satellite payload systems, particularly in the areas of satellite communication, standalone equipment control, payload thermal management, time calibration, command processing, and interface control. The system features rapid command response, high-reliability communication capabilities, and efficient parallel data processing, thereby enhancing overall system stability, reliability, and operational efficiency.

In the paper,the communication requirements of embedded systems and the characteristics of RapidIO bus communication are analyzed,the RapidIO network management technology is integrated in the rack,and a RapidIO virtual channel management method suitable for large-scale embedded heterogeneous platforms is proposed.Zynq chip is used as management nodes,RapidIO virtual channels are established.It provides high-speed communication capabilities for nodes within the rack for resource pool systems,and provides strong support for communication expansion of embedded systems.

The breaker,disconnector and other primary equipment in power equipment are getting closer to the secondary equipment.The sudden change of the electromagnetic field caused by switching operations of the primary equipment reduces the reliability of the secondary equipment.For example,the opening and closing operations of the disconnector in the substation generate strong transient electromagnetic pulses.Part of the energy carried by the electromagnetic pulse couples with the cable which is exposed outside of the secondary equipment,flows into the equipment,and interferes with the internal electronic devices.In severe cases,the strong transient electromagnetic pulses lead the device to fail and the equipment to work abnormally.In order to clarify the coupling mechanism of the electromagnetic pulse to the cable,the transient electromagnetic field generated by the switching operation of the disconnector in different voltage-level substations are measured in situ and collected,and the typical waveform of the pulse is extracted and reproduced approximately by a bounded-wave simulator in laboratory.The influence of the cable placement angle on electromagnetic coupling to the cable in bounded wave simulator is studied,which provides a reliability testing theory for chips worked in complex electromagnetic environment.

Human bone data is susceptible to interference factors such as light in the environment,resulting in high mean average accuracy (mAP) of the software's posture perception results.Therefore,a novel VR head display real-time attitude perception software based on optical tracking and motion estimation algorithms is proposed.The measurement system is composed of optical tracking equipment as the core to obtain real-time pose measurement data,and accurate pose information is obtained after error correction.By utilizing the OpenPose network to detect key points of human bones,and applying a motion estimation algorithm that introduces an early termination strategy to continuously search for real-time pose images,the best matching point is found while ignoring interference factors,in order to reflect the distribution position of motion vectors and recognize the current human pose.Finally,relying on a multi-layer perceptron network to achieve attitude classification,as the final output of temporal attitude perception results.The test results show that after combining optical tracking and motion estimation algorithms,the mAP value of the attitude perception results remains above 0.95,meeting the real-time attitude perception requirements of VR head display.

In order to meet the needs of the ground monitoring equipment to upload video data to the storage device quickly,solve the problem of analog decoding and data transmission of image sensor output PAL signal,this paper designs the PAL data input and network interface output hardware module based on FPGA.The PAL analog signal is converted into parallel digital signal by decoder,and the input data is cached by parity field data in FPGA,and the interlaced video output is realized by ping-pong operation.At the same time,in the way of calling MAC soft core inside FPGA,retransmission mechanism and asynchronous FIFO are added to UDP protocol to realize data network transmission.

A large number of optical transceivers are used in relay protection equipment for communication within and between devices.At present,the failure of optical transceivers can be mainly divided into two situations,and there are mature countermeasures for the complete failure of relay protection equipment.However,its incomplete failure may lead to serious problems such as single frame flashing of communication messages,false alarms,and network congestion,affecting the normal operation of relay protection equipment and having adverse effects on the entire system.This article focuses on the issue of incomplete failure of optical transceivers,and designs an optical port data monitoring mechanism based on FPGA chips to avoid the problem of abnormal optical transceivers leading to reduced reliability of relay protection equipment.A switching scheme is designed for the dual monitoring link,achieving seamless connection between A and B system monitoring.Finally,the effectiveness of the scheme is verified on the hardware platform.

In response to the current situation of massive network data volume, increasing attention and demands for network data confidentiality, an SM4 cipher coprocessor based on the Hummingbird E203 open-source RISC-V processor has been designed and implemented. Based on the Hummingbird E203 MCU platform, the SM4 cipher coprocessor has been extended through 5 custom extension instructions, allowing users to call the coprocessor core to encrypt and decrypt data by writing program code on the software side. Compared with no extension instructions, its throughput can reach 153.75 times. Simultaneously, by studying the SM4 encryption and decryption algorithm, implement module multiplexing for key extension and repeated encryption and decryption parts to reduce circuit area. Under the UMC 28 nm process, the combined area of the SM4 coprocessor is 7 098.8 μm², with a maximum clock frequency of 200 MHz and a data throughput rate of 775.758 Mbit/s. The SM4 coprocessor can achieve a data throughput rate of 150.588 Mbit/s at a clock frequency of 100 MHz.

Aiming at the problems of low transmission volume and slow speed of distribution automation communication in the process of transportation electricity,cloud edge collaboration mode and device to device (D2D) module are introduced to improve the communication structure between distribution automation equipment based on the industrial 4G Beidou distribution automation communication technology.Firstly,the relay communication network is built with the base station to improve the data transmission speed in the distribution network.Then,the security device manager (SDM) algorithm is improved,and the blocking characteristics of the channel are calculated by obtaining the bit error rate of each transmission channel.Finally,the blocking channel is modulated to make the transmission data more cooperative and further improve the transmission speed.The test results show that the maximum amount of communication detected by this system is 48 TB,and the average transmission speed is 10 MB/s,which indicates that this system has high applicability.

In response to issues such as abnormal degradation of chip performance caused by electromagnetic pulses in power application scenarios,and unclear failure mechanisms of devices such as MOSFET(Metal-Oxide-Semiconductor Field-Effect Transistors) within the chip,TLP (Transmission Line Pulse) pulses,with amplitude and width of 8 V and 100 ns,are applied into gate oxide layer of 5 V NMOS devices.The output characteristic curves I_d-V_d and the transfer characteristic curves I_d-V_g under different pulse cycles are measured.By calculating the device transconductance under different TLP number,the threshold voltage V_T and carrier mobility with TLP pulse are obtained.The test results show that under the same drain voltage V_d and gate voltage V_g, the drain current I_d of the device increases with the increase of the number of TLP pulses.TLP pulses cause a significant decrease of V_T,which decreases by about 25.66% under 20 000 TLP pulses,TLP pulses caused the V_T of the device to increase exponentially,and the fitting index is between 0.11~0.15.The influence of TLP pulses on the carrier mobility in the channel is not obvious.

The communication device,based on domestic FMQL as the main chip,needs to generate multiple high-speed clocks for other modules.The on-chip resources based on FMQL can generate several clocks,but there are some problems such as PL resource consumption,insufficient clock number,insufficient clock frequency,and insufficient flexibility in configuration.With the development of integrated circuits,using dedicated clock chips can effectively solve these problems.This paper proposes a method utilizing SI5341 and GM4526 clock chips to implement extended multi-channel high-speed clocks on the FMQL platform.The system design,hardware design and driver design of the method are introduced in this paper.The stability,practicability and flexibility of the method are verified by experiments.The method based on SI5341 and GM4526 to implement the extended multi-channel high-speed clock on the FMQL platform is stable,practical and flexible,providing reference for similar requirements.

In the paper, a software upgrade system is designed for communication power controllers. The system is developed based on the GD32F405RG chip, and the RS485 communication bus is used as the information transmission mode to receive the upgrade program during the APP stage. Then the correctness of the information transmission is verified by verification algorithms such as CRC, and then the upgrade program is stored in the off-chip memory chip W25Q128JVSQ and the communication power controller is restarted. During the BootLoader stage, the upgrade program is transferred to the internal FLASH of the GD32F405RG, and the update program proceeds to run after the verification is passed. The overall design and specific implementation methods of the system are described in detail. The test results show that the system successfully completes the software upgrade of the communication power controller within 15 minutes, and the communication power controller operates normally after the upgrade. This software upgrade method reduces the economic investment in upgrading the maintenance process of the communication power supply, and improves their sustainability and stability.

During the intelligent inspection of power lines, it is difficult to accurately identify the traces caused by power lines touching trees, and cannot provide a reliable basis for accident prevention and responsibility division. To solve these problems, the power line discharge trace identification method based on foreground area extraction and multi-feature decision fusion is proposed. Firstly, the experiment platform of contact tree discharge of medium voltage line is built, and the surface discharge trace is collected and the image set is constructed. Then, a de-shading algorithm combining texture sparsity and logarithmic transformation is proposed to eliminate the interference of shadow region. Furthermore, a target initial frame selection strategy combining global threshold and adaptive threshold segmentation is proposed, to address the problem that initial frame cannot be determined automatically in GrabCut algorithm. It realizes automatic and accurate segmentation of line trace under complex backgrounds. Finally, the texture and color features are extracted, and the power line trace recognition is realized by multi-SVM decision fusion. The experimental results show an average recognition accuracy of 88.39%, proving the effectiveness of the proposed method.

In response to the issue that the standard ST language cannot fully adapt to application scenarios such as wind turbine control,the article proposes and implements an extended ST language and its compilation system that integrates the characteristics of C language.The extended ST language integrates general recursive function,function without return value,dynamic array,function block array and calling program into the standard ST language.While fully compatible with the standard ST language,it compensates for the shortcomings of the standard ST language.The compiler system supports lexical analysis,parsing,semantic analysis and cross compilation of extended ST language,and generates executable files that can be recognized by the controller.The expanded ST language and its compilation system can fully adapt to wind power generation control and other application scenarios.After application in practical engineering,it has been shown that the extended ST language can fully support special applications in practical engineering and improve the writing and execution efficiency of control programs.

The manufacturing of circuit boards plays an important role in the life cycle of electronic product production,and in each process of circuit board production,quality control of circuit boards is the most important link.The FCT system is specifically used to inspect the quality of circuit board soldering.This article introduces a design scheme for a circuit boss FCT system based on a three-layer structure and multi task queue.Firstly,the composition and explanation of the hardware equipment of the FCT system are introduced.Then,the overall architecture of the upper computer software of the FCT system,the division of functional modules,and the detailed functions of each module are introduced.The outstanding technical implementation methods of the upper computer software in this scheme are emphasized,including the three-layer hierarchical pattern,ORM (Object Relationship Mapping), and multi task queue.Finally,a program flowchart of the FCT system's operation is provided.Through the hardware and software design of the FCT system,the problem of quality inspection of circuit boards has been perfectly solved.

This article introduces the protection and operational improvement of the Future Renewable Electric Energy Delivery and Management System (FREEDM),which uses solid-state transformers to connect residential AC and DC microgrids to the distribution system,and uses fault isolation equipment to isolate faulty lines.A current differential protection scheme is proposed to detect faults in the FREEDM based microgrid network,this method uses phasor measurement units for data synchronization and minimizes measurement errors,and uses IoT technology and Wi-Fi communication solutions for data monitoring and interconnection between devices.Then,a simulated FREEDM system is used for testing,and different types and fault resistances of faults are applied at different locations to demonstrate the effectiveness of the proposed protection method in detecting fault states.The performance of the proposed method is investigated using safety,reliability,and accuracy indicators.Finally,a prototype of the FREEDM system is designed,implemented,and tested using Proteus software simulator and laboratory.The results demonstrated the efficiency of the proposed protection scheme in detecting and isolating fault states in a fast,reliable,and accurate manner.In addition,the protection scheme achieved an accuracy of up to 98.825% for all faults.

Indoor location technology based on channel state information (CSI) has been widely used in various places,in the CSI phase fingerprint location scheme,the density of sampling points is closely related to the location effect.Due to the workload of data collection,previous scholars paid more attention to low-sampling density scenarios or adopted simulation methods to analyze sampling density research,which made it difficult to find the sampling density with the smallest positioning error.In this paper,the author first sets different CSI sampling densities,takes the CSI phase after data preprocessing as fingerprint characteristics,and then uses WKNN algorithm to analyze and explore the influence of different sampling densities on the positioning effect.The experiment results show that in the environment of 4 m×4 m,when a sampling point is taken every 0.4 m and the sampling density is 7.6 per square meter,the positioning accuracy is the highest,the average error is 0.34 m,and the sampling workload is taken into account.

A multi AGV path planning and scheduling control method based on Cyber Physical System (CPS) is proposed to address the complex implementation process, low path planning, and scheduling performance of the current Automated Guided Vehicles (AGV) logistics system. We have designed an AGV logistics system architecture that includes physical perception layer, network transmission layer, and control layer, and established a virtual path network model that reflects the imbalance status of cargos through time parameters. Considering time constraints, a multi AGV path planning method through an improved A * algorithm is proposed. A list based scheduling control algorithm has been proposed to avoid collision and conflicts among multiple AGVs. In the experimental phase, a simulation system is used to test the proposed method. The experimental results show that the sorting efficiency of the proposed method is about 1.3 times higher than D * planning and about 1.79 higher than A * planning. In addition, indicators such as average parking time, deadlock time, average global path occupancy rate, and average planning time have verified that the proposed algorithm offer lighter and more efficient computational efficiency, and it demonstrates significant potential for broad application in the field.

In this paper,a mainstream technology for manufacturing super junction MOS (SJMOS) devices,namely the Deep Trench Single Epitaxial Process (DTSE),is introduced.And the flow and characteristics of DTSE are described in detail.Based on the charge balance principle of SJMOS,the variation of breakdown voltage (BV) under different P-pillar doping concentrations is analyzed,revealing the reasons for the low BV.A improvement solution is proposed,and its feasibility is demonstrated through the experimental verification.

In order to cope with the increasingly severe challenge of waste classification, this paper designs a waste sorting device based on machine learning and vision algorithms. The device collects data from the video camera and sorts them by the Maix bit core board, in which the machine learning network MobileNet and the normalization algorithm in the vision module are applied to increase the sorting accuracy dramatically. After classification, the Maix bit core board communicates with the STM32F103 board to control the corresponding servo and the speech announce system to implement the sorting operation for the relevant type of waste. After experimental validation, this device can achieve garbage sorting speeds of less than 1 second and accuracy greater than 98%. Therefore, it possesses strong practicality in real applications.

For the new requirements of FPGA intelligence,dynamic and flexible in digital design applications,based on local dynamic reconfigurability,the logic function is abstracted into a hardware process similar to a software process,combined with the real-time task RT-Linux core to realize hardware process scheduling,and the FPGA local function backup and recovery technology is used to realize the real-time intermediate state backup,function interruption and overload switching and original function relay operation and recovery of the FPGA on-chip logic function by the operating system layer.Realize multi-task parallel switchable calls on FPGAs,and verify the hardware function thread scheduling and hardware process backup,switching,and recovery functions,so as to provide new design ideas and practical references for FPGAs to adapt to the cutting-edge digital system design of intelligence,efficiency,high dynamics and high plasticity.

This article proposes an improved plan for the SM3 algorithm using the agile development language BSV.By analyzing the algorithm's operating logic, the algorithm is innovatively split into multiple high-abstraction BSV modules, thereby effectively reducing the design complexity and making it comparable to traditional Verilog design. The code amount is reduced by 60% compared to the previous model. The iterative compression module has a greater impact on the algorithm performance, thus methods such as parallel pipeline and single-round logic optimization are employed for improvement from two aspects, and simulation verification is conducted on the Xilinx ARTIX-7 series FPGA platform with successful serial port debugging. The final results show that only 1 563 LUT resources are consumed to achieve a throughput of 3.2 Gbit/s, which represents up to a threefold improvement in throughput per unit logic resource compared to existing solutions. The maximum operating frequency reaches 375 MHz, with a higher practical value.

The reliability simulation of industrial-chip-featured LDMOS (Laterally Diffused Metal Oxide Semiconductor) devices under electromagnetic pulse (EMP) impact can be accomplished using the commercial TCAD (Technology Computer-Aided Design) software, which employs periodic TLP (Transmission Line Pulse) signals as transient input conditions for the degradation module. Due to the simplicity of this simulation, it is challenging to cover the common and complex EMP environments encountered by industrial chips. The expected device lifetime differs significantly from the empirical value, making it difficult to accurately assess the stability of chips. In this research, we combine the expectation-maximization algorithm and the reliability theory to optimize this process.Before conducting reliability simulations, the complex electromagnetic pulse signal is preprocessed to reduce the overall complexity. The preprocess significantly improves simulation efficiency and enhances the reliability of the modeling. The method can be integrated as a complementary module for mainstream TCAD simulation software when conducting electromagnetic field simulation, thereby improving the accuracy of reliability simulations for industrial chip devices.

Digital Signal Processing (DSP) chips are a class of microprocessors that boast lightning-fast computational speeds and an abundance of computational resources.Leveraging their exceptional processing capabilities,DSP plays an important role in the domains of image processing and high-performance computing in big data.Among the key technologies employed in DSP chip applications,self-starting technology stands out as a critical component.Moreover,high-performance DSP chips often integrate PCIe,a high-speed universal peripheral,to enhance their processing capabilities.In the article,we present a research that focuses on the design and implementation of a PCIe secure self-starting boot scheme for high-performance DSP chips.The secure solution holds significant potential for use in the development of high-performance DSP chips.

With the continuous improvement of embedded processor̓s performance,it is hard for the traditional parallel bus to satisfy the increasing requirement of bandwidth in embedded systems.RapidIO technology alleviates the contradiction between the traditional bus with slow development and the processor with high performance,meanwhile,network-on-chip have become the most commonly used interconnect structure in multi-core architectures.In order to realize the data interaction between RapidIO controller and network-on-chip,a conversion interface is designed,which can achieve the conversion of the RapidIO controller̓s AXI protocol to the internal packet transmission of the network-on-chip,and satisfy the needs of read/write operation of the RapidIO device.The simulation results show that the function of the conversion interface is correct and complete,and meets the design requirements.

The rapid development of contemporary information technology not only brings convenience to people, but also creates many security risks. With the rapid development of the Internet and the Internet of Things, the number of globally connected devices is growing rapidly, and "Internet of Things" has become an important direction for the future development of global networks. However, the prosperity of edge IoT proxy devices has also given rise to diverse security issues. However, traditional security protection mechanisms have become inefficient on existing edge IoT proxy devices. However, the trusted execution environment is too large and relies on remote authorization and other issues. At present, there are common security risks in applications such as being cracked, data being stolen and tampered with, posing a great threat to financial data security, personal privacy data protection, and business data integrity.This article proposes a lightweight memory protection unit based on the RISC-V architecture,implementing a hardware secure boot mechanism based on hardware trusted roots.By extending the RISC-V instruction set and using newly added instructions to create a memory secure space, the general memory is converted into a secure encrypted space, achieving a trusted embedded system.

Unstructured data resources contain great research value.With the expansion of the application range of information technology and internet technology,the scale of unstructured data resources increases,which poses a great challenge to its storage technology.A rapid storage method for large-scale unstructured data resources is proposed.The hierarchical clustering algorithm is used to group unstructured data resources.Taking a group of unstructured data resources as the object,combining the transmission distance,node energy,transmission direction and other factors of data resources,the forwarding path of unstructured data resources is determined,the storage process of unstructured data resources is described,and the storage mechanism of hierarchical expansion is formulated,so as to realize the rapid storage of large-scale unstructured data resources.The experimental data shows that the maximum storage rate of unstructured data resource obtained by the proposed method is 1 920 MB/s under different experimental conditions,and the maximum storage location accuracy of unstructured data resource is 98%,which fully confirms the better application performance of the proposed method.

A design method and circuit of the interface between DSP and ARINC429 bus controller based on FPGA are given.This design method is also suitable for the interface expansion design of DSP and serial controller,CAN controller,etc.Firstly,the main signals and timing of TMS320C6713 EMIF and HI-8582 are analyzed,and the analysis shows that the communication between TMS320C6713 and HI-8582 can be realized by implementing decoding logic and timing control through FPGA.Then the detailed hardware design and the interface logic design are discussed.Then the ARINC429 bus driver software design is discussed.Finally,the stable and reliable work of the interface circuit is verified through environmental test and practical application.

To address the security concerns regarding the transmission of data from embedded devices in contemporary Internet of Things networks, a novel scheme for MQTT-based trusted device authentication and secure data transmission has been devised by leveraging TrustZone technology. This scheme enhances the MQTT communication protocol and includes the design of prototypes for gateways and data acquisition devices that communicate via this protocol. Device identity authentication, alongside data encryption and tamper-resistance during transmission, are achieved through the implementation of a hybrid domestic commercial cryptography algorithm. The integration of TrustZone technology facilitates the isolation of software and hardware elements within the gateway system, thereby safeguarding the secure storage of critical information such as keys and lists of trusted devices. Both theoretical security analysis and empirical testing demonstrate that the proposed solution effectively elevates the security of privacy data transmission and storage in IoT embedded contexts, aligning well with practical application requirements.

A dynamic management method for RapidIO nodes based on port-write event triggering is proposed to address the issues of low real-time management and CPU resource occupancy in large-scale integrated electronic information systems.This method utilizes the port-write packet of the RapidIO switching chip to report the information of nodes that have retired or entered the network,and dynamically manages all nodes in the RapidIO network through this information.The actual engineering application results show that this method has high real-time performance and low CPU resource consumption.

This article focuses on the site selection problem for high-speed railway stations. By collecting information from multiple high-speed railway stations, mathematical models are established using MATLAB, SPSS, Excel software, incorporating theories of mathematical statistics and intelligent algorithms. An evaluation system for site selection criteria is established, including factors such as distance from the city center, distance from the airport, passenger flow, and others. The BP neural network algorithm is applied to calculate the comprehensive evaluation matrix. By comparing the success and failure cases of Guangzhou South and Shenyang South, the accuracy of the model results is confirmed. This article also explores the specific implementation of high-speed railway station site selection. Taking the Dan-Jin of the high-speed railway as an example, the article successfully determines the site selection location by establishing an objective function of minimizing economic costs and relevant constraints. Considering the passenger travel convenience and construction costs in high-speed railway station site selection, optimal coordinates and minimum total costs are obtained through a genetic algorithm. The mathematical model proposed in this article has the characteristics of objectivity, accuracy, and strong practicality.

In order to solve the problems of low measurement accuracy and poor algorithm adaptability in industrial measurement of part dimensions,a machine vision parts measurement system based on super-resolution model and improved Canny algorithm is designed and proposed.Firstly,the camera is calibrated to obtain the proportional relationship between the pixel distance and the actual size.Secondly,a super-resolution model is introduced and improved to pre-process the input image to obtain an image with clearer edge details.Thirdly,in order to solve the edge detection problem caused by poor lighting conditions in the industrial measurement environment,the Otsu algorithm and the double threshold segmentation algorithm are combined,and the Canny edge filtering algorithm is improved by using local threshold segmentation to obtain edge images.Finally,after simultaneously performing circle fitting and straight line fitting on the edge image,the part size results are marked based on the camera calibration results and super-resolution model parameters.The experiment results show that the measurement accuracy of this system can reach 0.001 mm,the average measurement error is 0.007 4 mm,and the overall measurement speed is 6.44 s,which can meet the needs of high-precision industrial measurement.

The conventional automatic delay control methods for fiber optic communication networks have shown inadequate suppression effects on communication interference. Therefore, signal sequence prediction and buffer algorithm are proposed for automatic delay control in fiber optic communication networks. A prediction objective function is established to predict the communication signal sequence using load adaptive scheduling method. Based on the buffer algorithm, the density of optical fiber network communication is calculated. Allocate communication density according to the coding format. Suppress communication interference based on allocation parameters. Set sampling time intervals, allocate communication data packets, and achieve delay control in fiber optic communication networks. The experimental results show that the designed method can control the delay of fiber optic communication within 0.89 ns, indicating good control effectiveness.

To resolve the issue concerning the susceptibility of the prevailing three-dimensional digital compasses in the market to external magnetic field interference during the detection of Earth's magnetic field,resulting in diminished measurement precision,a three-dimensional digital compass system employing the Tunnel Magnetoresistance (TMR) effect and grounded in the least squares method has been devised.The error characteristics of a three-dimensional digital compass in practical environments is studied.After being corrected by ellipsoidal fitting,the least squares method is used for error compensation.The azimuthal precision prior to compensation stood at 4.18°,whereas post-compensation,it reached 0.46°.This reflects a tenfold enhancement in accuracy,substantially mitigating azimuthal discrepancies within the three-dimensional digital compass.The empirical findings demonstrate that the utilization of the least squares approach substantially heightens the precision of three-dimensional digital compass systems,underscoring its substantial utility in engineering applications.In addition,given the high sensitivity characteristics of TMR sensors,they are extremely suitable for use in space,indicating that the system has extremely high application value.

To address the problems of low efficiency, heavy workload and one-sidedness of the traditional single-point measurement, this study proposes a building model reconstruction method based on 3D laser scanning technology. Firstly, a ground 3D scanning system is used to obtain the 3D building model, from which target feature points are extracted. Then, the RANSAC algorithm is combined with European clustering method to segment the building facade, meeting the requirements of building digitization. In this study, the building facade information can be accurately extracted by preprocessing the 3D data, and using semi-automatic filtering to denoise and plane fitting. The experimental results show that the proposed model produces less noise, has superior plane fitting performance, with an accuracy of about 99%, which can achieve the purpose of fine building modeling.

Aiming at the problem that the railway terminal equipment cannot access the TSN network at present,a TSN gateway equipment design scheme based on single chip microcomputer and TSN chip is proposed,so that the equipment has the TSN capability,so as to ensure the deterministic transmission of train control data and improve the safety of train operation when the train multi-network integrates a large amount of data.

In response to the current problems of short lifespan and high cost in storage devices, we chose to use the domestic microcontroller GD32 to reduce the cost, and adopted the equalization loss algorithm to extend the memory lifespan, and designed a high-capacity data storage system. The system takes GD32 as the control core, with two pieces of NAND Flash as the storage media, connected through the EXMC interface that comes with GD32, and uses two RS422 to communicate with the host computer for data: one way to transmit the storage data, and the other for the command control. The host computer manages the storage status and controls the wear and tear of the NAND Flash block through the balanced loss algorithm. After testing, the system reaches a storage capacity of 32 GB, and a writing speed of 1 MB/s. The service life of NAND Flash is improved, ensuring stable performance and meeting the requirements for long-term, high-capacity data storage.

The high-performance DSP+FPGA architecture can meet the real-time processing requirements of the embedded image processing system for large amounts of data and complex algorithms. The traditional DSP+FPGA architecture uses the parallel external memory interface as the data transfer interface, with a large number of traces, difficult PCB wiring, and many failure points. The use of high-speed serial buses can solve the above problems. This paper proposes an image processing system based on high-speed serial buses and DSP+FPGA architecture. PCIe bus is used as the image data channel between DSP and FPGA, SRIO bus is used as the link between DSP and DSP, and SGMII bus is used as the data channel between DSP and PHY chip. High-speed serial buses enable faster the data transfer rate, easier layout of the PCB, lower electromagnetic interference, and better noise immunity. The system designed in this paper has been deployed and operated stably in practical locations, which demonstrates that the design is feasible and the system is reliable.

During the dynamic tests on a structural model using wind tunnel experiments, it is necessary to store, record, and analyze the status information of multiple test processes using a data recorder. The data recorder utilizes an LVDS (Low Voltage Differential Signaling) interface. To facilitate the issuance of commands and playback tests with an upper computer during the ground phase, an LVDS to Ethernet test fixture was designed. This device employs an FPGA (Field-Programmable Gate Array) as the main control chip, utilizing 8B/10B encoding and decoding to ensure the stability of signal transmission over the LVDS line. Communication with the upper computer is achieved through an Ethernet interface. Data from the recorder is transmitted via LVDS to RAM in the FPGA, and dual RAM buffering is used to enhance transmission efficiency. Subsequently, the data in the RAM is encapsulated into Ethernet UDP/IP frame format. On the basis of the UDP protocol, a command-data "handshake" operation is achieved through alternating dual RAM buffers. CRC (Cyclic Redundancy Check) verification and data retransmission methods are used to reduce the error rate during transmission. Finally, the data is sent to the upper computer through a physical layer chip. Validation has shown that data transmission using LVDS, FPGA, and Ethernet is feasible, with good stability and reliability, making it suitable for practical engineering applications.

To address the shortcomings of traditional defogging algorithm and meeting the real-time requirements of the defogging system, an improved defogging algorithm is proposed and designed with FPGA. Firstly, a Gaussian low-pass filter is employed to retain the low-frequency information of the image. Secondly, the rough transmittance map of the foggy image is obtained by combining the a priori theory of the dark channel with the bilateral filtering to acquire the refined transmittance map. Lastly, the dehazed image is obtained by the foggy imaging model. Additionally, the improved algorithm is optimized with FPGA. The experimental results show that the improved defogging algorithm enhances the defogging effect on images with high-brightness areas compared to other defogging algorithms. When performing video image defogging on an FPGA platform, it can achieve a speed of 60 frames per second, meeting the real-time requirement.

In this paper, a novel class-F voltage doubler rectifier is proposed for radio frequency energy harvesting (RFEH). In the proposed structure, two different harmonic termination networks are employed to block the harmonics of voltage doubler diodes and reshape current waveform and voltage waveform. Thus, the power conversion efficiency (PCE) of the conventional voltage doubler rectifier can be improved significantly. For validation, a prototype is fabricated and measured. The measured peak PCE is 76.5% with a 13 dBm input power and a 1 600 Ω load. Besides, the input power for PCE is higher than 50%, ranging from 1.8 to 15.5 dBm.

With the rapid development of very large-scale integration IC manufacturing process and the continuous improvement of integration, the difficulty of chip timing convergence has become increasingly prominent. The significance of timing, as one of the core indexes in the physical design of digital chips, cannot be underestimated. In integrated circuit design, buffers are added to optimize fan-out and reduce interconnect latency, thereby improving timing performance. However, due to the limitations of EDA tools in predicting the position of standard cells, the method of automatically inserting buffers may be unreasonable. This study conducted an in-depth exploration of the placement and route design of an ASIC chip using Innovus as a design tool. During the placement stage, an optimized method targeted at buffer insertion was employed. The experimental results indicate that this method significantly improved the design result after placement and route, accelerating the time sequence convergence process.

Based on an FPGA hardware platform, a laser line scanning camera captures images of the linear laser beam projected onto the surface of the measured object, subsequently extracting the two-dimensional pixel coordinates of the laser line using the center-point method to reconstruct the spatial coordinates of the end face contour parallel to the light axis of the measured object. Addressing the issue of non-continuous laser line images in this system due to equipment and environmental factors, this paper proposes a Lagrange interpolation algorithm based on FPGA, to fit the discontinuous laser line pixel coordinate curves. The algorithm includes sub-modules for floating-point addition, subtraction, multiplication, division, comparison, and sequential loop control, fully leveraging the parallel processing capability of the FPGA to accelerate image processing algorithms, thereby offering higher fitting precision compared to linear interpolation methods. The experiment results demonstrate that the computation time of this module is 7.945 microseconds, achieving a 76-fold speed improvement over an 8-core 64-bit computer, ensuring the real-time performance of the system while realizing high-precision fitting, thus enhancing the overall system stability.

To address problems such as wide distribution and lack of centralized management of distributed photovoltaic power stations, a monitoring system for distributed photovoltaic power station based on LoRa and NB-IoT is designed. The system collects temperature, humidity, light intensity, voltage, current and other data of distributed photovoltaic power station through wireless terminal nodes, and then carries out networking through LoRa wireless communication technology. Once the collected data is aggregated at the gateway, it is uploaded to the OneNET cloud platform using NB-IoT wireless technology allowing the user side to retrieve cloud platform data to monitor the distributed photovoltaic power plants. The experiment results show that the system with stable operation for extended periods is cost-effective and offers flexible networking, which can satisfy the monitoring requirements of power stations.

A high-precision positioning watch based on intrinsic safety is designed and implemented to address issues such as inconvenient rescue in emergencies due to portable positioning tags placed at the waist in coal mines, lack of LCD display for escape route information, and difficulty in perceiving vibrations. The battery output of the watch adopts a three-level protection to achieve higher explosion-proof safety grade. The heart rate monitoring sensor is used to collect the heart rate status of workers entering the well in real-time, monitor their physical health status. UWB positioning technology and tunnel base station are used for real-time distance measurement, and the positioning accuracy is improved from meter level to centimeter level. Through UWB communication network, the watch can achieve two-way communication with the ground dispatch room. In emergency situations, one click underground rescue is required, and when gas exceeds the limit, evacuation information is received from the ground. Additionally, it features an LCD display for showing escape route information, and provides multi-functional alerts including sound, light, and vibration, thereby significantly enhancing safety for miners during underground operations.

This paper analyzes the failure phenomenon of a high-density packaged product for spacecraft under random vibration in the aerospace environment. Based on the structural model and application conditions of this product, a finite element simulation model is established. The results of simulation and failure analysis indicate that the device breaking bond wire under vibration loads undergo fatigue damage and instantaneous fracture in two steps, causing device failure. Based on this analysis, models with different bond wire lengths were established and simulated under random vibration conditions of spacecraft.

A peritoneal dialysis machine is a medical device used to infuse dialysate into the abdominal cavity of a patient, complete dialysis through the peritoneum, and then extract the fluid out of the abdominal cavity. In order to ensure the stable and reliable quality of the peritoneal dialysis machine and prevent harm to the life safety of patients, this project conducted scientific research on the key parameters of the peritoneal dialysis machine, such as pressure, temperature, flow rate and capacity, to ensure the traceability of the core parameters, and develop a set of intelligent peritoneal dialysis machine detection device. This will enable the construction of an automated calibration system for peritoneal dialysis machines under a big data platform.