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Review of digital phase-locked loop technology development for frequency modulated continuous wave systems
CHEN Yongli, JI Zichuan, XIAO Yan, ZONG Jiaming
Integrated Circuits and Embedded Systems ›› 2025, Vol. 25 ›› Issue (5) : 35-44.
PDF(4452 KB)
PDF(4452 KB)
Review of digital phase-locked loop technology development for frequency modulated continuous wave systems
This article first introduces three main requirements of a phase-locked loop (PLL) for Frequency Modulated Continuous Wave (FMCW) radar systems: frequency modulation bandwidth, frequency modulation slope, and linearity. Then, based on highly cited and influential articles from the past decade, it analyzes the advantages and application challenges of digital phase-locked loops (DPLL) in FMCW systems and briefly outlines the existing methods to overcome these challenges. The development trends of phase-locked loops in relation to the three main requirements are summarized, and a new figure of merit definition is proposed to evaluate the performance of PLLs for FMCW systems. Finally, it is pointed out that digital phase-locked loops are a key research direction for developing high-performance FMCW systems in the future.
Digital phase lock loop / DPLL / FMCW / digital predistortion
| [1] |
|
| [2] |
德州仪器. 毫米波雷达传感器基础知识, 2017.
|
| [3] |
|
| [4] |
|
| [5] |
ROBERT BOGDAN STASZEWSKI,
|
| [6] |
|
| [7] |
|
| [8] |
|
| [9] |
PRATAP TUMKUR RENUKASWAMY,
|
| [10] |
|
| [11] |
|
| [12] |
|
| [13] |
P T RENUKASWAMY. A 16GHz, 41kHzrms Frequency Error,Background-Calibrated,Duty-Cycled FMCW Charge-Pump PLL[J]. ISSCC, 2023(2):74-75.
|
| [14] |
|
| [15] |
|
| [16] |
|
| [17] |
|
| [18] |
|
| [19] |
|
| [20] |
|
| [21] |
|
| [22] |
|
| [23] |
|
| [24] |
|
| [25] |
|
| [26] |
|
| [27] |
|
| [28] |
|
| [29] |
|
| [30] |
|
| [31] |
|
| [32] |
|
| [33] |
|
| [34] |
|
| [35] |
|
| [36] |
|
| [37] |
|
| [38] |
|
| [39] |
|
| [40] |
|
| [41] |
ALAHDAB, MANTYNIEMI, KOSTAMOVAARA. A 12-bit digital-to-time converter (DTC) with sub-ps-level resolution using current DAC and differential switch for time-to-digital converter (TDC)[C]// Instrumentation & Measurement Technology Conference.IEEE, 2012.DOI:10.1109/I2MTC.2012.6229685.
|
| [42] |
|
| [43] |
|
| [44] |
|
| [45] |
|
| [46] |
|
/
| 〈 |
|
〉 |