Design and Verification of a First-Level Configurable Instruction Cache for High-Performance DSPs

Integrated Circuits and Embedded Systems ›› 0

Integrated Circuits and Embedded Systems ›› 0 DOI: 10.20193/j.ices2097-4191.2025.0004

Design and Verification of a First-Level Configurable Instruction Cache for High-Performance DSPs

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{{article.zuoZheEn_L}}. {{article.title_en}}[J]. {{journal.qiKanMingCheng_EN}}, 0 https://doi.org/10.20193/j.ices2097-4191.2025.0004

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