Trusted execution technology for processors is a viable solution for protecting sensitive information,providing a secure and isolated environment for sensitive information processing to ensure information security and privacy protection.However,trusted execution technology for processors faces threats from various attacks.To systematically understand the research on vulnerability exploration in processor trusted execution technology,this paper first introduces trusted execution technologies such as SEV in AMD,SGX in Intel and TrustZone in ARM.Then,the methods of vulnerability research under different processor platforms are introduced.Finally,this paper discusses the potential applications of trusted execution technology in the field of industrial control system,and forecasts its role in ensuring the security of industrial control systems and points out directions for future research.
Physical Unclonable Functions (PUFs) can be regarded as a "chip fingerprint" with lightweight, unpredictable, and difficult to clone characteristics, and have become an important component of IoT hardware security mechanisms. However, the implementation of traditional PUFs requires the addition of FPGA or dedicated integrated circuits at the hardware level, which will increase hardware costs. For billions of existing IoT embedded devices, it is difficult to increase PUF security attributes through hardware modifications. Therefore, we discuss the promising method to implement these intrinsic PUFs on commercial off-the-shelf devices and explore the potential applications of intrinsic PUFs. We will provide a systematic review of existing IPUFs, particularly Memroy based Intrinsic PUFs (MIPUFs), and discuss the feasibility and future development directions of IPUFs in existing systems, in order to promote the engineering application of this technology.
Electromagnetic fault injection (EMFI) has become an effective fault injection attack technique threatening integrated circuit (IC) security.Existing research has demonstrated that EMFI perturbs circuits' internal states by inducing parasitic current on the IC power grid.Finite element analysis of the power grid under EMFI shows that the induced current could increase the IR drop of the power grid,leading to circuit faults.Therefore,to address this problem,we propose a power supply port placement optimization approach which reduces the effect of the induced current.The experiment results show that by optimizing the positions of the power supply ports,the worst IR drop can be reduced by 40%,enhancing the robustness of the power grid.
Aiming at the potential security issues arising from the existing deep learning edge applications relying on non-domestic FPGA architectures and encrypted IP implementations,which are difficult to quickly deploy on domestic FPGA platforms with insufficient IP and still under development,a neural network hardware deployment framework towards domestic FPGA is designed to achieve secure,autonomous and controllable deployment of domestic FPGA neural networks.In addition,the fast pipelined convolutional circuit and the im2col conversion circuit are designed to rapidly compute the systolic array.The experimental results demonstrate that the framework is capable of generating networks,such as Lenet5,with up to 147.8 GOPS for 16-bit data type and 0.024 ms running time,which represents a 5.13x improvement in throughput and a 6.67x decrease in time,respectively.An evaluation of im2col operation on RTL design yields up to 124.9x gains over CPU on Intel Xeon E-2276M.
Post-quantum cryptography has become a research hotspot in the current security field. In this paper, a secure SoC design scheme based on post-NIST quantum cryptography is proposed by studying Saber algorithm, which is a candidate of post-NIST quantum cryptography competition. The scheme firstly analyzes the hardware architecture of the algorithm, optimizes operations such as matrix operation and numerical splicing to improve hardware efficiency, and uses secondary verification to enhance the security of the decryption process of the algorithm, design Hash random number expansion generation module, encryption and decryption module and data storage and random number seed generator to complete the Saber algorithm hardware IP Core. On the basis of RISC-V processor, bus and interface circuit, a secure SoC based on post-quantum cryptography is designed with clock gating technology. The experimental results demonstrate that the area of the designed security SoC chip is 2.6 mm2, with an equivalent logic gate count of 90k. The chip core area accounts for 75.2%, the PAD area accounts for 24.8%, and the chip power consumption is 9.467 mW.
The traditional switched-capacitor (SC) capacitance-to-digital converter (CDC) based on SAR ADC uses high-voltage power supply to increase output swing in order to achieve a high capacitance detection range. However, to maintain noise performance, they require high current drive, significantly increasing system power consumption. To address the above issues, this article proposes a capacitance-to-digital converter based on a digital amplifier, which uses the CDAC array as the analog output to bear high voltage. Only the CDAC array and sensing capacitors are driven by high voltage (5 V), while the rest is still powered by low voltage (1 V), allowing the CDC to achieve high dynamic range and sensitivity while maintaining low power consumption and low noise. In addition, for the optimization of noise, this work achieves first-order noise shaping for SAR ADC by adding an integral loop in the digital amplifier, reducing the quantization noise of the system and improving the effective number of bits for CDC. On the other hand, by introducing active noise cancellation (ANC) technology, the system's aliasing noise is reduced and the signal-to-noise ratio is improved.
In order to cope with the increasingly severe challenge of waste classification, this paper designs a waste sorting device based on machine learning and vision algorithms. The device collects data from the video camera and sorts them by the Maix bit core board, in which the machine learning network MobileNet and the normalization algorithm in the vision module are applied to increase the sorting accuracy dramatically. After classification, the Maix bit core board communicates with the STM32F103 board to control the corresponding servo and the speech announce system to implement the sorting operation for the relevant type of waste. After experimental validation, this device can achieve garbage sorting speeds of less than 1 second and accuracy greater than 98%. Therefore, it possesses strong practicality in real applications.
The conventional automatic delay control methods for fiber optic communication networks have shown inadequate suppression effects on communication interference. Therefore, signal sequence prediction and buffer algorithm are proposed for automatic delay control in fiber optic communication networks. A prediction objective function is established to predict the communication signal sequence using load adaptive scheduling method. Based on the buffer algorithm, the density of optical fiber network communication is calculated. Allocate communication density according to the coding format. Suppress communication interference based on allocation parameters. Set sampling time intervals, allocate communication data packets, and achieve delay control in fiber optic communication networks. The experimental results show that the designed method can control the delay of fiber optic communication within 0.89 ns, indicating good control effectiveness.
To address the problems challenges such as high flight altitude, large changes in target scale, and the densely occluded targets, the study utilizes deep learning methods for target detection and identification and visual localization of UAV. A UAV target detection and positioning system is designed and discussed in depth. The study selects Yolov5 deep learning network model for target detection, completes end-to-end training prediction based on Darknet deep learning framework, and finally utilizes AprilTag visual benchmark library to complete the auxiliary localization of UAV's spatial positioning. The test results show that the parameter count of Yolov5 model is only 5.3. Meanwhile, the model achieves a precision of 97.41%, a recall rate of 90.73%, and an mAP of 83.2. The fitting precision of AprilTag assisted localization is more than 95%. The research and design of intelligent UAV vision system based on deep learning not only has actual engineering values, but also significant societal importance.
To address the problems of low efficiency, heavy workload and one-sidedness of the traditional single-point measurement, this study proposes a building model reconstruction method based on 3D laser scanning technology. Firstly, a ground 3D scanning system is used to obtain the 3D building model, from which target feature points are extracted. Then, the RANSAC algorithm is combined with European clustering method to segment the building facade, meeting the requirements of building digitization. In this study, the building facade information can be accurately extracted by preprocessing the 3D data, and using semi-automatic filtering to denoise and plane fitting. The experimental results show that the proposed model produces less noise, has superior plane fitting performance, with an accuracy of about 99%, which can achieve the purpose of fine building modeling.
A multi AGV path planning and scheduling control method based on Cyber Physical System (CPS) is proposed to address the complex implementation process, low path planning, and scheduling performance of the current Automated Guided Vehicles (AGV) logistics system. We have designed an AGV logistics system architecture that includes physical perception layer, network transmission layer, and control layer, and established a virtual path network model that reflects the imbalance status of cargos through time parameters. Considering time constraints, a multi AGV path planning method through an improved A * algorithm is proposed. A list based scheduling control algorithm has been proposed to avoid collision and conflicts among multiple AGVs. In the experimental phase, a simulation system is used to test the proposed method. The experimental results show that the sorting efficiency of the proposed method is about 1.3 times higher than D * planning and about 1.79 higher than A * planning. In addition, indicators such as average parking time, deadlock time, average global path occupancy rate, and average planning time have verified that the proposed algorithm offer lighter and more efficient computational efficiency, and it demonstrates significant potential for broad application in the field.
An adaptive neuro-fuzzy inference system (ANFIS)-based method for correcting outliers in power demand curves is proposed for outliers in smart grid big data. The method performs big data analysis for smart meters in smart grids to detect and correct zero-value anomalies in timing data. The effectiveness of the proposed method is verified using real power demand data, and the results show that the ANFIS method is able to correct the outliers with higher accuracy compared with the linear interpolation and artificial neural network based methods, with a maximum relative error of only 3.76%. In addition, the standard deviation of the relative error is also smaller at 2.26%. The experiment results show that the ANFIS method fully combines the advantages of fuzzy logic system and neural network, effectively dealing with the outliers in the peak hour power load demand curve well. This provides a valuable reference for further improving the effect of smart grid big data analysis.
