The inherent capacitor mismatch resulting from process variations is a significant impediment in the designing of high-resolution Analog-to-Digital Converters. Various calibration methods have been previously introduced, often employing additional circuits or external controllers, albeit at the expense of increased silicon area or intricate operational complexities. In this work, we have established the relationship between capacitor mismatches, output deviation, and Total Harmonic Distortion (THD) in capacitor Digital-to-Analog Converters. Consequently, the statistical distribution of expected THD under certain mismatch can be derived. After that, we propose a new compensation strategy that adopts the Dynamic Element Matching (DEM) technique to conventional cyclic ADCs with minimum hardware cost and implement this compensation scheme in a cyclic-pipelined ADC. We reassess the performance of the proposed ADC based on the formulated theory. Importantly, the measurement results of the cyclic ADC have not only confirmed the validity of our proposed theory but also demonstrated the robust performance of the simplified version of the DEM algorithm. This work is constructive for performance estimation in other high-precision ADC designs.
In this paper, a novel class-F voltage doubler rectifier is proposed for radio frequency energy harvesting (RFEH). In the proposed structure, two different harmonic termination networks are employed to block the harmonics of voltage doubler diodes and reshape current waveform and voltage waveform. Thus, the power conversion efficiency (PCE) of the conventional voltage doubler rectifier can be improved significantly. For validation, a prototype is fabricated and measured. The measured peak PCE is 76.5% with a 13 dBm input power and a 1 600 Ω load. Besides, the input power for PCE is higher than 50%, ranging from 1.8 to 15.5 dBm.
In the face of the problems of hardware development constraining software development, hardware resource constraints, and insufficient testing in the application of embedded development boards in the aerospace field, virtualization solutions are introduced for the hardware platform on which a certain type of flight control software depends. Firstly, an AArch64 instruction test set was written to verify the credibility of QEMU dynamic translation, and Flash was successfully mounted by debugging, tracing, changing, and compiling the QEMU source code. Secondly, a new equipment simulator was created, the network communication mode of the model machine was adjusted, and the virtual machine, simulator and model machine were jointly debugged to ensure the normal data transmission, so as to smoothly build a virtual platform. Furthermore, an integrated development environment is designed to support functions such as the visual construction of the virtual platform, remote debugging of source code, target code coverage statistics and to improve the convenience and reliability of the virtual platform. Finally, it is observed that the simulation results of a certain type of flight control software are consistent on both the real platform and the virtual platform, verifying that the virtual platform is real and usable.
To address the shortcomings of traditional defogging algorithm and meeting the real-time requirements of the defogging system, an improved defogging algorithm is proposed and designed with FPGA. Firstly, a Gaussian low-pass filter is employed to retain the low-frequency information of the image. Secondly, the rough transmittance map of the foggy image is obtained by combining the a priori theory of the dark channel with the bilateral filtering to acquire the refined transmittance map. Lastly, the dehazed image is obtained by the foggy imaging model. Additionally, the improved algorithm is optimized with FPGA. The experimental results show that the improved defogging algorithm enhances the defogging effect on images with high-brightness areas compared to other defogging algorithms. When performing video image defogging on an FPGA platform, it can achieve a speed of 60 frames per second, meeting the real-time requirement.
With the rapid development of very large-scale integration IC manufacturing process and the continuous improvement of integration, the difficulty of chip timing convergence has become increasingly prominent. The significance of timing, as one of the core indexes in the physical design of digital chips, cannot be underestimated. In integrated circuit design, buffers are added to optimize fan-out and reduce interconnect latency, thereby improving timing performance. However, due to the limitations of EDA tools in predicting the position of standard cells, the method of automatically inserting buffers may be unreasonable. This study conducted an in-depth exploration of the placement and route design of an ASIC chip using Innovus as a design tool. During the placement stage, an optimized method targeted at buffer insertion was employed. The experimental results indicate that this method significantly improved the design result after placement and route, accelerating the time sequence convergence process.
Based on an FPGA hardware platform, a laser line scanning camera captures images of the linear laser beam projected onto the surface of the measured object, subsequently extracting the two-dimensional pixel coordinates of the laser line using the center-point method to reconstruct the spatial coordinates of the end face contour parallel to the light axis of the measured object. Addressing the issue of non-continuous laser line images in this system due to equipment and environmental factors, this paper proposes a Lagrange interpolation algorithm based on FPGA, to fit the discontinuous laser line pixel coordinate curves. The algorithm includes sub-modules for floating-point addition, subtraction, multiplication, division, comparison, and sequential loop control, fully leveraging the parallel processing capability of the FPGA to accelerate image processing algorithms, thereby offering higher fitting precision compared to linear interpolation methods. The experiment results demonstrate that the computation time of this module is 7.945 microseconds, achieving a 76-fold speed improvement over an 8-core 64-bit computer, ensuring the real-time performance of the system while realizing high-precision fitting, thus enhancing the overall system stability.
The high-performance DSP+FPGA architecture can meet the real-time processing requirements of the embedded image processing system for large amounts of data and complex algorithms. The traditional DSP+FPGA architecture uses the parallel external memory interface as the data transfer interface, with a large number of traces, difficult PCB wiring, and many failure points. The use of high-speed serial buses can solve the above problems. This paper proposes an image processing system based on high-speed serial buses and DSP+FPGA architecture. PCIe bus is used as the image data channel between DSP and FPGA, SRIO bus is used as the link between DSP and DSP, and SGMII bus is used as the data channel between DSP and PHY chip. High-speed serial buses enable faster the data transfer rate, easier layout of the PCB, lower electromagnetic interference, and better noise immunity. The system designed in this paper has been deployed and operated stably in practical locations, which demonstrates that the design is feasible and the system is reliable.
A peritoneal dialysis machine is a medical device used to infuse dialysate into the abdominal cavity of a patient, complete dialysis through the peritoneum, and then extract the fluid out of the abdominal cavity. In order to ensure the stable and reliable quality of the peritoneal dialysis machine and prevent harm to the life safety of patients, this project conducted scientific research on the key parameters of the peritoneal dialysis machine, such as pressure, temperature, flow rate and capacity, to ensure the traceability of the core parameters, and develop a set of intelligent peritoneal dialysis machine detection device. This will enable the construction of an automated calibration system for peritoneal dialysis machines under a big data platform.
To address problems such as wide distribution and lack of centralized management of distributed photovoltaic power stations, a monitoring system for distributed photovoltaic power station based on LoRa and NB-IoT is designed. The system collects temperature, humidity, light intensity, voltage, current and other data of distributed photovoltaic power station through wireless terminal nodes, and then carries out networking through LoRa wireless communication technology. Once the collected data is aggregated at the gateway, it is uploaded to the OneNET cloud platform using NB-IoT wireless technology allowing the user side to retrieve cloud platform data to monitor the distributed photovoltaic power plants. The experiment results show that the system with stable operation for extended periods is cost-effective and offers flexible networking, which can satisfy the monitoring requirements of power stations.
This paper analyzes the failure phenomenon of a high-density packaged product for spacecraft under random vibration in the aerospace environment. Based on the structural model and application conditions of this product, a finite element simulation model is established. The results of simulation and failure analysis indicate that the device breaking bond wire under vibration loads undergo fatigue damage and instantaneous fracture in two steps, causing device failure. Based on this analysis, models with different bond wire lengths were established and simulated under random vibration conditions of spacecraft.
During the dynamic tests on a structural model using wind tunnel experiments, it is necessary to store, record, and analyze the status information of multiple test processes using a data recorder. The data recorder utilizes an LVDS (Low Voltage Differential Signaling) interface. To facilitate the issuance of commands and playback tests with an upper computer during the ground phase, an LVDS to Ethernet test fixture was designed. This device employs an FPGA (Field-Programmable Gate Array) as the main control chip, utilizing 8B/10B encoding and decoding to ensure the stability of signal transmission over the LVDS line. Communication with the upper computer is achieved through an Ethernet interface. Data from the recorder is transmitted via LVDS to RAM in the FPGA, and dual RAM buffering is used to enhance transmission efficiency. Subsequently, the data in the RAM is encapsulated into Ethernet UDP/IP frame format. On the basis of the UDP protocol, a command-data "handshake" operation is achieved through alternating dual RAM buffers. CRC (Cyclic Redundancy Check) verification and data retransmission methods are used to reduce the error rate during transmission. Finally, the data is sent to the upper computer through a physical layer chip. Validation has shown that data transmission using LVDS, FPGA, and Ethernet is feasible, with good stability and reliability, making it suitable for practical engineering applications.
A high-precision positioning watch based on intrinsic safety is designed and implemented to address issues such as inconvenient rescue in emergencies due to portable positioning tags placed at the waist in coal mines, lack of LCD display for escape route information, and difficulty in perceiving vibrations. The battery output of the watch adopts a three-level protection to achieve higher explosion-proof safety grade. The heart rate monitoring sensor is used to collect the heart rate status of workers entering the well in real-time, monitor their physical health status. UWB positioning technology and tunnel base station are used for real-time distance measurement, and the positioning accuracy is improved from meter level to centimeter level. Through UWB communication network, the watch can achieve two-way communication with the ground dispatch room. In emergency situations, one click underground rescue is required, and when gas exceeds the limit, evacuation information is received from the ground. Additionally, it features an LCD display for showing escape route information, and provides multi-functional alerts including sound, light, and vibration, thereby significantly enhancing safety for miners during underground operations.
