Neural network models demand high processor performance and energy efficiency. The memory-computing integrated architecture is an energy-efficient solution. This paper introduces a digital interface simulation scheme to address simulation verification challenges in analog memory-computing integrated designs and improve simulation efficiency in large-scale computing scenarios. The scheme analyzes SRAM-based memory-computing integration and combines the SPICE model with a digital control circuit. This enables the use of digital methods for simulation and verification, potentially boosting development efficiency. An evaluation system comparing the digital interface simulation with traditional analog circuit simulation reveals that the new solution increases simulation speed by more than 2 times and configuration efficiency by more than 1 000 times. This research is supported by the key research and development program of the ministry of science and technology (2021YFB3601300), and this research has been validated with tape-out at the 180 nm process node, demonstrating the efficiency advantages of the digital interface simulation scheme for memory-computing integrated design in large-scale computing.
Using HKN201 of Xiangteng Micro as the core, a real-time, highly concurrent and high-performance edge-end embedded intelligent computing system has been constructed. Combining the design concept of high-speed circuits and practical engineering applications, the basic design methods and effective control measures for power integrity and signal integrity are provided, and simulation analysis is carried out with simulation results given. Finally, application tests are conducted on this system and performance indicators are presented. The experimental results show that this scheme exhibits universality, high scalability, and high reliability, providing references for the research on intelligent products.
High-precision TDC requires a multiphase clock with low jitter and low latency to ensure its normal operation. Therefore, a variety of key technologies have been adopted to optimize the design of core modules such as the structure of the DLL system, charge pump, voltage-controlled delay line, and lock detection circuit. Sub-gate-level delay line technology enables DLL systems to generate multi-phase clock signals with a delay of only 1.25 ps. The design of the three-level structure enables the DLL system to get rid of the reliance on high-precision and high-frequency reference clock signals, and it can work normally using a 100 MHz reference clock signal. The application of technologies such as current steering and dual clamping can effectively suppress the influence of non-ideal effects such as charge sharing and channel length modulation, and effectively improve the performance of static phase error and peak-to-peak jitter. Based on the 65 nm process of TSMC, this paper has completed the design, simulation and wafer fabrication verification of the circuit. The simulation results show that the DLL system can achieve the set functions. The post-simulation results are as follows: The static phase error is approximately 13.1 ps, the peak-to-peak jitter performance is approximately 1.01 ps, and the system power consumption is 82.5 mW. Ultimately, the test results show that the frequency range of the system is approximately 50~320 MHz, and the locking time is approximately 117.5 μs.
This paper proposes a compact model of fully depleted silicon-on-insulator (FDSOI) based on single transistor pixel sensor (1T-PS) which is affected by total ionizing dose (TID) effects. This model takes into account the generation of fixed charges within the buried oxygen (BOX) layer and interface states at the surface below BOX. The corresponding relationship between irradiation dose and threshold voltage degradation of 1T-PS can be obtained through this model. By integrating the model into BSIM-IMG and executing the typical image input layer of an artificial neural network, the impact of the TID effects on the accuracy of 1T-PS arrays performing vector matrix multiplication (VMM) is studied. The test results indicate that after exposure to a total ionizing dose of 600 krad (Si), the recognition accuracy decreases to approximately 85%.
Due to the high risk of neonatal jaundice and the limitations of traditional monitoring methods, a wearable dynamic jaundice level and physiological parameter monitoring system has been designed to meet the clinical demand for non-invasive dynamic jaundice detection equipment. The system includes a forehead-mounted wireless physiological signal collector, a Bluetooth communication host and a data analysis platform based on LabVIEW. The system uses the highly integrated MAX86916 optical sensor to synchronously collect four-channel photoplethysmography (PPG) signals, and obtains bilirubin, heart rate, and blood oxygen saturation data through signal processing. The nRF52832 microcontroller with Bluetooth Low Energy (BLE) protocol is used for wireless communication. The data is transmitted wirelessly to the Bluetooth communication host, and then uploaded to the LabVIEW program of the PC via USB for display and storage. To verify the functionality and performance of the system, basic parameter tests, and comparative tests of each physiological parameter with commercial instruments were conducted in sequence. The device (13.5 g, 41 mm×29.7 mm×15.1 mm) can continuously monitor for 5 hours. The detection range of the bilirubin prediction model is 1~13 mg/dL. Measurements demonstrated bilirubin, heart rate and blood oxygen are in strong agreement with standard instruments (p>0.05). And the maximum absolute errors for bilirubin, HR, and SpO2 measurements are 0.96 mg/dL, 1 bpm, and 2.1%, respectively. Moreover, the system can sensitively track the decrease in heart rate after exercise and the variations in blood oxygen during breath-holding.The experiment results show that the system is effective in monitoring jaundice, heart rate and blood oxygen level. It features lightweight design, wearability, multi-parametric detection, and non-invasive dynamic measurement capabilities. After further optimization, it is expected to be applied in neonatal clinical monitoring.
Focusing on the data acquisition challenges of SSI protocol absolute encoders, this study proposes a method to directly acquire data from SSI protocol absolute encoders using DSP's SPI interface or McBSP interface. The system employs the TMS320F28335 as the master control chip and designs an interface circuit between the DSP and the SSI protocol absolute encoder. By properly configuring the registers of the DSP's SPI and McBSP interfaces and processing the interface data, the objective of directly obtaining 13-bit SSI protocol absolute encoder data via the DSP is achieved. This method can be extended to DSP-based acquisition of SSI protocol absolute encoder data of any bit-length, demonstrating strong practical applicability.
PowerPC460 is a 32-bit embedded processor that supports hard floating-point mode. It features a set of 32-bit general-purpose registers and 64-bit floating-point registers. The GCC compiler generates a supporting toolchain for this professor. By default, when handling data operations, the GCC toolchain leverages the floating-point registers to access 64-bit integer data. This approach effectively reduces the number of operation instructions and the overall register usage, enhancing computational efficiency. However, challenges arise from the disparity in data alignment between floating-point and general-purpose registers. When floating-point registers are utilized for integer data processing, the accessed memory address must strictly comply with the bit-width requirements of the data type. Failure to meet this alignment criterion can lead to runtime alignment exceptions. Moreover, when the operating system performs context switching for integer operation tasks, it requires additional protection support for the data in floating-point registers. This requirement incurs additional overhead, degrading system performance. To address these issues, this article presents an optimized strategy for the instruction generation module of the GCC compiler. The proposed method advocates using general-purpose registers to execute 64-bit integer data operations in the hard floating-point mode. Additionally, a new compilation option is introduced, retaining the original global optimization scheme. A domestically produced embedded operating system is experimentally deployed at the PowerPC460 board level for functional and performance testing. The results indicate that, while maintaining correct functional behavior, the optimized approach achieves approximately a 6.3% improvement in task switching time, demonstrating its practical value in enhancing system performance.
Aimed at the problem of data noise interference in bridge bearing tilt angle and stress monitoring, a real-time monitoring data preprocessing system based on Kalman filtering is designed. The system uses classical Kalman filtering algorithm to preprocess the tilt angle and stress data collected by the sensor, which effectively suppresses the noise interference. Based on the parallel computing advantage of FPGA, the functions of data acquisition, filtering and transmission are realized, and the monitoring data of bridge bearings are dynamically displayed in real time combined with the upper computer. The experimental results show that the signal-to-noise ratio of the filtered stress signal is 32.10 dB, the mean square error is 0.051 8, the correlation coefficient is 0.581 1, and the variance ratio is 0.701 8. The SNR, MSE, correlation coefficient and variance ratio of inclination signal after filtering are 33.98 dB, 0.041 8, 0.703 2 and 0.629 1, respectively, indicating that the filtering algorithm can effectively suppress noise interference. The developed system exhibits remarkable stability and reliability, achieving rapid data processing ability meanwhile satisfying the needs of real-time monitoring of bridge bearing inclination and stress. Additionally, this paper uses ASIC process to design the Kalman filter algorithm chip, and realizes the Kalman filter circuit based on 180 nm CMOS process. The clock frequency is 160 MHz, and the comprehensive area is 599 131 μm2.
With the rapid development of Industrial Internet of Things (IIoT) and smart sensing technologies, the importance of pipeline pressure monitoring has become increasingly prominent in fields such as oil, natural gas, water utilities, and urban heating. This paper designs an intelligent pipeline monitoring meter head, aiming to achieve high-precision, real-time, and intelligent pipeline pressure monitoring. The monitoring meter head integrates advanced sensor technology, a low-power wireless communication module, and an embedded data processing system, enabling real-time collection, transmission, and analysis of pipeline pressure data. The monitoring meter head employs a high-precision MEMS pressure sensor combined with a temperature compensation algorithm to ensure measurement accuracy and stability. It is equipped with an embedded microprocessor capable of data preprocessing and anomaly detection. Additionally, it supports the RS485 communication protocol and standardized interfaces, facilitating integration with other systems. The experimental results demonstrate that the intelligent pipeline monitoring meter head achieves superior performance in measurement accuracy, communication range, and power consumption, meeting the practical requirements of industrial applications.
To enhance the real-time performance, scalability, and reliability of CT detector nodes, and satisfy the bus communication requirements of the current slip ring equipment, a CT detector CANopen node design method is proposed. The proposed method involves hardware node design using the XMC4000 series micro-controller to build the hardware platform, as well as adaptation of hardware drivers and a real-time operating system. A customized object dictionary is designed to include command control and status feedback. By optimizing the state machine and message task flow, the real-time performance is improved. The test results show that the functionality complies with the CANopen protocol specifications, and the electrical characteristics meet the requirements for voltage, edge transition, and bit width testing. Additionally, under continuous transmission of 5 156 frames, the success rate reaches 100%, demonstrating high reliability. The bus delay maintains within 480 ns, ensuring favorable real-time performance. The designed object dictionary can be reused and transplanted in CT systems with different hardware platforms, effectively supplementing the current medical device configuration file (CiA-412).
This paper introduces a clock system based on MCU, including the components, as well as the advantages and disadvantages of the clock system. A clock architecture suitable for automotive electronic MCU is proposed, and the overall design framework is given. The working principle of the system and the relationship between the system clock and power consumption are analyzed in detail, and the clock design related to functional safety is described. Under the 40 nm process library for rail technology, the circuit is simulated using EDA tool and applied in the CKS32K1XX chip project.
