A power integrity analysis is conducted for the layout and routing design of a domestic power verification board targeting a 48 V power input, with an output voltage of 0.8 V and a current requirement of 1 000 A. A simulation design strategy based on the power distribution network (PDN) is proposed. In the initial stage, an optimal layout is selected by comparing the voltage drop simulation results with different PCB layouts. Then, through simulation analysis of the power plane and via current carrying capacity, the vias are optimized. The optimization measures significantly reduced the voltage drop by 14.5 mV, decreased the plane circuit density by 61%, lowered power system loss by 17.2 W, and halved the via current. Moreover, the thermal effect of using a heat sink is simulated, and the results show that the highest temperature dropped by 27.81 ℃ after the application of the heat sink. Finally, using power plane resonance simulation analysis, the power plane resonance noise is successfully controlled within 0.001% of the output voltage. After board fabrication and actual measurement, the ripple noise of the verification board was controlled within 1% of the rated output voltage, and the overall efficiency exceeded 90%, reaching an industry-leading level. The results indicate that the simulation process strategy proposed in this paper can effectively improve the efficiency of PCB design, and avoid power integrity risks, such as excessive voltage drop loss, overcurrent, and overheating.
The travel and daily activities of visually impaired individuals typically rely on guide dogs, walking sticks, or assistance from others. However, with the advancement of economic development, urban planning is becoming increasingly dense. The complexity of urban layout and road design has significantly increased. Consequently, these traditional methods are no longer sufficient to meet the daily needs of blind individuals. Therefore, it is crucial to prioritize attention towards the visually impaired community and enhance their quality of life. This design focuses on machine vision techniques for denoising, filtering, and target calibration in color information and depth images. Subsequently, machine learning training is employed to achieve image-based functions such as color recognition, obstacle detection, and distance measurement. The analysis results are then converted into audio signals which are outputted through voice feedback to provide users with walking suggestions while alerting them about obstacles that cannot be observed in advance. The ultimate goal is to offer obstacle avoidance services for visually impaired individuals by minimizing the impact of unforeseen obstacles during mobility.
Unlike Artificial Neural Networks (ANN), Spiking Neural Networks (SNN), as a representative of the third generation of neural network technologies, perform computations based on biological neuron mechanisms, using sequences of spike signals to transmit information. This exhibits significant energy efficiency advantages and high-speed processing capabilities for massive data. However, due to the complex dynamics of spiking neurons and the non-differentiability of spike computations, the current direct training methods for SNNs are not very effective, hindering their widespread application. At present, converting high-precision ANN to SNN is considered one of the most promising methods for generating SNN. However, mainstream ANN-to-SNN conversion methods have their limitations: first, they do not support negative spikes, making it difficult to represent negative spikes from dynamic vision sensor cameras; second, low latency and high precision cannot be achieved simultaneously during the conversion process. To address these issues, this paper proposes a novel spiking neuron that can represent the entire range of values, supporting both positive and negative values in traditional ANN as well as the positive and negative polarities of DVS (Dynamic Vision Sensor) spikes. Additionally, this paper proposes a step-wise Leaky ReLU activation function and a regional convergence testing algorithm to achieve zero-error conversion from ANN to SNN. With these methods, we realize a high-precision, low-latency, and robust ANN-to-SNN conversion. Our method demonstrates outstanding performance on the CIFAR10 and CIFAR100 datasets.
In the development of embedded test platforms, real-time capability that enables the platform system to respond swiftly to task events. In most cases, there are numerous tasks of different types running on the platform, hence the challenge of ensuring the real-time execution of tasks with multiple and diverse relationships.To address, this paper proposes a multi-DAG real-time priority scheduling algorithm (MDRTPS). This algorithm is mainly divided into three steps: firstly, real-time task separation for multiple DAGs, where the separated real-time task set and the normal task set use different priority algorithms and resource allocations. Secondly, Maintainance of three scheduling queues to coordinate the ordering between different DAG tasks. Fianlly, the scheduler assigns tasks to the processor core based on the earliest completion time. Experimental results show that the MDRTPS algorithm outperforms the HEFT algorithm and CPOP algorithm in terms of task span and response speed of real-time tasks.
To address the issues of high resource utilization and poor customizability associated with using pre-built AXI interface IP cores, a phased, self-designed approach is proposed to add AXI bus support to a designed MIPS processor core. The design is implemented using Verilog HDL for writing RTL code. The overall logic functionality of the processor was verified in the Vivado simulation environment, and the bitstream file was downloaded to the FPGA development board for prototype verification to obtain utilization and timing. Finally, the processor is synthesized using the Design Compiler (DC) tool, and the overall area and power consumption of the processor are evaluated. The verification results indicate that the self-designed AXI bus consumes fewer resources and occupies less area compared to directly using an AXI interface IP core. Furthermore, this approach ensures that the AXI bus is added without changing the processor core architecture, significantly reducing the difficulty of replacing the original interface in the processor core with the AXI bus interface. It not only reduces integration complexity but also ensures a high degree of customization to meet specific system requirements and performance demands.
The analog source holds an important position in the test and calibration system of radio radar equipment. The beacon machine equipped with a certain type of Doppler radar has defects such as being bulky and heavy, and being unable to simulate Doppler signals, making it difficult to meet complex test requirements. Therefore, a small dynamic analog source based on the implementation of FPGA is designed. This analog source, through the collaborative operation of FPGA and digital DAC, achieves rapid frequency adjustment, enabling the carrier signal to superimpose Doppler information. In addition, the signal frequency and amplitude control methods of the analog source are flexible control methods, allowing for both wireless real-time adjustments and output according to pre-stored data. It can not only be adjusted wirelessly and in real-time but also output according to pre-stored data. This effectively compensates for the deficiencies of the original beacon machine and provides strong support for the test and calibration of radar equipment.
A new denoising algorithm for frequency hopping signals based on intrinsic time-scale decomposition (ITD) is proposed to address issues such as low signal-to-noise ratio, difficulty in analysis and reconstruction. The algorithm takes ITD as its core, and uses the decomposition processing to obtain the sudden change characteristics of the cross-correlation peak values between the rotation component, trend component and the original signal to establish noise discrimination criteria, accurately removing noise components to achieve frequency hopping signal reconstruction and signal-to-noise ratio improvement. The simulation results demonstrate the effectiveness of the algorithm, which can adapt to a signal-to-noise ratio of -1 dB while ensuring that the distortion of the reconstructed signal is less than 5%. The reconstructed signal can be improved by at least 9 dB.
T-gate PMOS devices are increasingly essential in RFSOI circuits due to their remarkable radiation resistance and low parasitic capacitance. Conductance is a key parameter for MOS devices. However, the conductance of T-gate PMOS devices exhibits a double-peak effect as the gate voltage increases, affecting the judgment of circuit development. In this paper, the internal mechanism of the double-peak effect of the conductance of T-gate PMOS devices is thoroughly analyzed by combining experimental data and 3D TCAD simulation results. The influence of the double-peak effect on the conductance is discussed from the perspectives of temperature, main gate size, and sub-gate size. Finally, based on the layout structure of the T-gate PMOS device, an improved result is proposed to suppress the double-peak effect. The proposed solution has been verified by simulation and wafer test and can be highly applicable to the circuit design of T-gate PMOS structures in the SOI process.
The traditional RF power supply of the mass spectrometer is driven by crystal, and its frequency is fixed and nonadjustable, making the debugging of the RF power supply inconvenient in the development stage. A signal source system for RF power supply by using direct digital frequency synthesis (DDS) and embedded technology is designed in order to resolve the deficiency. The system is composed of DDS chip and STM32 series microcontroller based on ARM. It can output sine wave signal in single and sweep mode by the control of upper computer. The scanning range of this system is 100 kHz~1 MHz with the precision better than 0.02% under 1 MHz. It can serve as a signal source for multiple RF power supplies. The experiment results show that the Ion trap RF power can output peak-to-peak voltage up to 3.5 kV and resonant frequency 1.013 6 MHz by the drive of the system.
Due to the vast quantity and intricate structure of electronic archives, designing efficient data storage and retrieval schemes for cross-domain searches is imperative to enhance retrieval accuracy. In this regard, research has been conducted on a cloud storage-based secure cross-domain retrieval algorithm for electronic archive data. Under optimal storage nodes, the proposed algorithm employs cloud storage nodes to distribute an electronic archive file to different regional storage nodes. It leverages a hierarchical principle to calculate distances between cross-domain nodes and determines the number of cloud storage nodes through threshold grading, achieving tiered storage of electronic archive data. Additionally, this study adopts the Fourier transform method to eliminate duplicate data within electronic archives, thereby boosting retrieval efficiency. The algorithm defines the retrieval space for electronic archive data by measuring the average correlation between the clustering center and all electronic archive data. It then determines satisfaction vectors, assesses the satisfaction level of electronic archive data within the retrieval space, and applies gradient methods to refine these satisfaction vectors. By correlating user search keywords, precise and secure cross-domain retrieval of electronic archive data is achieved. Compared to location-index-based retrieval algorithms and HBase-based retrieval methods, this algorithm exhibits superior self-correlation retrieval performance for electronic archive data, capable of elevating cross-domain secure retrieval precision to over 90%.
At present, a single positioning technology cannot achieve good positioning results both indoors and outdoors simultaneously. For example, Beidou positioning technology can achieve high accuracy in outdoor positioning, but its performance in indoor positioning is poor. Bluetooth has high positioning accuracy in indoor positioning but is less effetive in outdoor positioning. Based on the above situation, this paper proposes an indoor and outdoor collaborative positioning technology based on Beidou and Bluetooth positioning. The Beidou and Bluetooth positioning systems are unified in the same coordinate system, and an improved BP neural network is used to achieve seamless switching in all scenarios. At the same time, a positioning fusion strategy is introduced for indoor and outdoor buffer areas to improve positioning accuracy. The experiment results show that in all scenarios, the average positioning error of the collaborative positioning system has increased by 0.7%, 31.7% and 2.4% compared to a single positioning system, respectively, proving the effectiveness and accuracy of the method.
