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  • Cover Article
    YANG Yihao, LIU Guoao, YU Jianrui, MA Jinge, HU Yuanqi
    Integrated Circuits and Embedded Systems. 2024, 24(12): 1-11. https://doi.org/10.20193/j.ices2097-4191.2024.0056

    The inherent capacitor mismatch resulting from process variations is a significant impediment in the designing of high-resolution Analog-to-Digital Converters. Various calibration methods have been previously introduced, often employing additional circuits or external controllers, albeit at the expense of increased silicon area or intricate operational complexities. In this work, we have established the relationship between capacitor mismatches, output deviation, and Total Harmonic Distortion (THD) in capacitor Digital-to-Analog Converters. Consequently, the statistical distribution of expected THD under certain mismatch can be derived. After that, we propose a new compensation strategy that adopts the Dynamic Element Matching (DEM) technique to conventional cyclic ADCs with minimum hardware cost and implement this compensation scheme in a cyclic-pipelined ADC. We reassess the performance of the proposed ADC based on the formulated theory. Importantly, the measurement results of the cyclic ADC have not only confirmed the validity of our proposed theory but also demonstrated the robust performance of the simplified version of the DEM algorithm. This work is constructive for performance estimation in other high-precision ADC designs.

  • Integrated Circuits and Embedded Systems. 0, 24(10): 0. https://doi.org/10.20193/j.ices2097-4191.2024.0035
    This study developed a Field-Controlled Enhancement Backside-Illuminated Single-Photon Avalanche Diode (SPAD) device using a simulation design platform. By adjusting the electric field in the avalanche region of the backside-illuminated SPAD, the photon detection efficiency was further improved, and the dark count rate was reduced. Simulation results indicate that the SPAD design effectively enhances electron multiplication efficiency through the synergistic effect of horizontal and vertical electric fields, achieving a peak detection efficiency of 50.1%. At an excess bias voltage of 3V, the dark count rate decreased to 764 Hz. The study compares and analyzes the effects of different depletion layer thicknesses and P-Well radii on the performance of the field-controlled enhanced backside SPAD device, determining the optimal structural dimensions. The results provide a new technical approach for high-precision photoelectric detection applications based on SPAD and lay the groundwork for further development and application of SPAD technology in scientific research and industrial applications.
  • Cover Article
    CUI Shouyi, YANG Guowei, HE Yuheng, GUAN Jingxuan, HU Yuanning, LIAO Dandan, JING Kai
    Integrated Circuits and Embedded Systems. 2024, 24(8): 1-6. https://doi.org/10.20193/j.ices2097-4191.2024.0009

    To address the demands of digital acquisition of vital signs signals and continuous blood pressure prediction,this paper designs and constructs a continuous blood pressure prediction system based on two-dimensional (2D) convolution.The system hardware adopts ESP32 module,AD8232 module and PulseSensor sensor to collect the human electrocardiography (ECG) and photoplethysmography (PPG) signal data,which are then transmitted to the server through the MQTT protocol for the consequent processing.Regarding the algorithms of this paper,a neural network model using ECG and PPG signals was designed and trained to predict continuous human blood pressure,employing the Gramian angular difference field (GADF),2D convolution,and model pruning techniques.The performance of the continuous blood pressure prediction model is verified on both classic open-source datasets and self-collected datasets.This system proposed in this paper provides a practical reference scheme for the vital signs signal acquisition and continuous blood pressure prediction.

  • Cover Article
    LIU Shanshan, JIN Hui, LIU Sijia, WANG Tianqi, ZHOU Bin, MA Yao, WANG Bi, CHANG Liang, ZHOU Jun
    Integrated Circuits and Embedded Systems. 2024, 24(6): 1-8.

    Voting-based classifiers are widely used in many A.pngicial Intelligence (AI) applications.In their implementation,memories that store all known data are prone to suffer different effects like radiation and physical variations,causing soft errors and can even change the classification results.Therefore,error-tolerance must be achieved in these memories for safety-critical applications.Existing error-tolerant techniques commonly utilize error correction codes,however,the memory redundancy they introduce further increases the burden of storage.In this paper,a redundancy-free technique is proposed by focusing on the impact of errors on the classification performance,instead of the error itself.It can recover the error-free classification results under errors by exploiting the flipped data.A k nearest neighbor classifier is taken as a case study to evaluate the proposed technique.The simulation results show that the proposed scheme offers almost full error tolerance without incurring any memory redundancy,moreover,it significantly reduces the hardware overheads for protection circuits compared to existing techniques.

  • Cover Article
    YANG Lihong, LI Shixin, HAN Chenxi, YUN Yueheng, LIU Shubin, ZHAO Xiaoteng, ZHU Zhangming
    Integrated Circuits and Embedded Systems. 2024, 24(4): 1-9.

    In high-speed wireline communication,clock-forwarding receivers requires the de-skew circuit to achieve the optimal sampling relationship between the clock and the data,and to ensure the synchronization of multiple data channels.A global de-skew scheme is proposed in the paper,which only uses one data and clock channel for alignment,and implements multi-channel data synchronization by clock delay matching and distribution techniques,reducing the power and area overhead by the independent de-skew circuit for each channel.The proposed receiver consists of 8 data channels,1 half-rate forwarded clock channel,and a global de-skew circuit based on the delay-locked loop.Based on 180 nm CMOS technology,at a data rate of 2.5 Gb/s,it can remove any skew between the input clock and data,and obtain the sampling phase at the center of the data eye,with the ability of clock duty cycle calibration.At a supply voltage of 1.8 V,the total power consumption of the proposed receiver is 187 mW,occupying the area of 0.16 mm2,saving 45.2% and 62.8% of power and area overhead,respectively,compared with the independent de-skew scheme for each channel.

  • Research Paper
    WANG Menghao, ZHAO Xiaoteng, DONG Zhicheng, ZHANG Miao, LIU Shubin, ZHU Zhangming
    Integrated Circuits and Embedded Systems. 2024, 24(3): 27-34.

    High-speed extra short reach (XSR) wireline interfaces are an important technical solution for chiplets interconnection.The traditional continuous time linear equalizer (CTLE) based on current mode logic (CML) has gradually failed to meet the demand for high-density,miniaturization,and low-power consumption of chiplet data interfaces due to the use of high supply voltage and passive components.To address this problem,this paper proposes an inverter-based CTLE with mid-frequency compensation (MFC) to transmit 28 Gb/s non-return to zero (NRZ) signals as well as 56 Gb/s 4-level pulse amplitude modulation (PAM4) signals in XSR applications.The design is implemented in a 28 nm CMOS process with a core area of only 400 μm2.After an XSR channel at -9.4 dB@14 GHz,the post-layout simulation results show that the proposed CTLE improves the eye width of the 28 Gbaud NRZ and PAM4 signals by 0.14 UI and 0.41 UI,and the eye heights by 328 mV and 119 mV,respectively.The power consumption is 6.12 mW at 56 Gb/s PAM4 signaling.

  • Research Paper
    ZHANG Zhanhua, WANG Jiahao, DING Wenjie, CAO Peng
    Integrated Circuits and Embedded Systems. 2024, 24(2): 57-63.

    With the evolution of advanced technology,the proportion of leakage power consumption in the total power consumption of integrated circuits continues to increase,which has gradually become one of the important factors restricting the reduction of circuit power consumption.Among the existing leakage power optimization methods,the method based on threshold voltage allocation has an exponential power optimization effect and has no influence on the layout and routing,so it is widely adopted.However,in commercial signoff tools,in order to maintain pseudolinear complexity,the global search made by the underlying algorithm is limited,which makes it difficult to obtain optimal results.In this paper,a joint optimization framework RL-LPO based on graph neural network and reinforcement learning is proposed to achieve efficient gate unit threshold voltage distribution.In RL-LPO,the timing and physical information of the graph neural network GraphSAGE encoding circuit are used to aggregate the target unit and its local neighborhood information.Using the Deep Deterministic Policy Gradient (DDPG) reinforcement learning algorithm,the threshold voltage allocation is carried out considering the leakage power consumption and timing variation under the guidance of the reward function.The gate unit threshold voltage distribution framework RL-LPO proposed in this paper is verified by IWLS2005 and Opencores reference circuits under the 28 nm process,and compared with commercial signoff tools,RL-LPO reduces the additional leakage power consumption by at least 2.1% and achieves at least 4.2 times acceleration without adding timing violations.

  • Research Paper
    NI Wenwei, ZUO Yunfan, YAN Hao
    Integrated Circuits and Embedded Systems. 2024, 24(2): 64-69.

    Sparse matrix solving is an important part of SPICE simulation.The operators currently used for solving are usually general-purpose floating-point calculation units.In order to solve the problem of double-precision floating-point speed in SPICE simulation,this article improves the addition/subtraction and multiplication units in general floating-point operators to enable faster solution speed in the context of SPICE simulation.The rounding parallel delay optimization algorithm and dual-path design scheme are used for the traditional addition and subtraction unit,and the critical path delay of the circuit is optimized by means of Shannon expansion and inexact leading zero compensation.For the traditional multiplication unit,the related delay is improved by changing the traditional compression topology layer structure and optimizing logic such as rounding and carry in the injection value algorithm.In the end,the double-precision floating-point solution achieved delays of 0.46 ns and 0.79 ns respectively under the TSMC 28 nm process.Compared with Synopsys' DW library unit,the delays are reduced by 33.4% and 7.1% respectively,and the area is reduced by 4.62% and 1.6% respectively.The experiment results show that the improved floating-point unit can effectively reduce the time of a single matrix solution step and accelerate the overall speed of transient simulation to a certain extent.

  • Overview
    DENG Zhonghan
    Integrated Circuits and Embedded Systems. 2024, 24(1): 1-12.

    Integrated circuit technology is one of the core technologies of modern electronic engineering,which promotes the development of the entire science and technology industry.Starting from the whole industrial chain of integrated circuits,this paper briefly introduces the current situation of integrated circuit technology and industrial chain at home and abroad from four perspectives:device technology,manufacturing equipment,design tools and chip categories.In the future,with the advancement of technology and the growth of application demand,integrated circuits will continue to play a key role in promoting the sustainable development of the industry.It is hoped that this paper can inspire domestic counterparts,enrich the understanding of the current situation of the industry,and provide a certain reference value for the determination of the direction and goal of scientific research and application.

  • Research Paper
    BAI Zixing, DAI Huasheng, SONG Yijing, JIANG Jinhu, ZHANG Weihua, LIANG Hao
    Integrated Circuits and Embedded Systems. 2024, 24(1): 58-63.

    With the trend of digitization,intelligence,and networking sweeping the world,functional security and network security are increasingly intertwined and overlapping,evolving into endogenous security issues.The operating system is an important component of computer systems and the cornerstone of software architecture,and operating system level endogenous security is crucial.The dynamic heterogeneous redundant architecture based on mimetic defense is a key technology for achieving endogenous security in operating systems.However,it currently faces challenges such as single kernel operating systems not supporting endogenous security,lack of operating system level endogenous security solutions,and incomplete design of operating system level consensus mechanisms.This article analyzes and designs an embedded security architecture for operating systems,heterogeneous redundancy mechanisms,efficient communication,and consensus mechanisms,and proposes a multi kernel based embedded security technology solution for operating systems.

  • TOPICAL DISCUSS
    Wu Xiaoze, Li Qingfeng, Niu Jianwei
    Integrated Circuits and Embedded Systems. 2023, 23(12): 4-7.
    This paper explores the key technologies of an industrial robot operating system based on a mixed criticality system to address the technical challenges faced by robots in non-structured or semi-structured intelligent scenarios.With the rapid application of intelligent technologies in the field of robotics,the robot operating systems need to meet the requirements of strong real-time tasks for control systems and weak real-time tasks for intelligent applications.So a heterogeneous multi-core intelligent system is needed.The paper proposes an architecture design specifically tailored for robots,with the aim of enhancing the real-time performance,security,and intelligence level of robot operating systems.Furthermore,this paper provides insights into the future development trends of industrial robot operating systems and predicts the future evolution direction.
  • TOPICAL DISCUSS
    Wen Feng, Guo Hongwei, Li Huijing, Yang Zhiwen
    Integrated Circuits and Embedded Systems. 2023, 23(12): 8-11.
    Aiming at the problem of occasional power loss that may occur in the complex environment of the bomb shipboard memory,a memory solution with power failure rewrite function is proposed to avoid the last stored data being overwritten by the new data after the memory recovers from the occasional power loss on the bomb arrows.The power down-surviving technique is implemented on the basis of write-while-erase,and cross-biplane programming is used to satisfy the data writing rate.The ground test bench simulates the data sent from the bomb system,and after a large number of tests,the results show that the design achieves the function of power failure renewal,and can achieve the stable storage of data,which verifies the reliability of the system.