To break the bottleneck that low transform efficiency between square matrix and vector (or between series port and parallel port) severely limits the transportation and processing velocity of audio/video signals, in this study design and verification of a high-performance 64-bit SoC hardware logic architecture was carried out based on FPGA technology. This study mainly focuses on exploring hardware logic arithmetic for flatten transformation of 8×8-bit binary square matrix, unflatten of 64-bit vector and precise matching clock tree, with auxiliary subsystems architected including I/O FIFO and simple center processing unit. A novel "64-bit asynchronous congregation direct-latch" logic combined with "synchronous serial-parallel shifting" is proposed to eliminate clock redundancy. By further implementing dual-channel logic and PLL-based frequency multiplication, the processing latency is compressed to its physical limit. Experimental results show that the latency is reduced from 72 base clock cycles to as low as 1 base clock cycle, achieving a 9-to-72 times throughput enhancement. This research provides robust hardware support for high-speed edge computing and real-time control systems.

Lookup-table (LUT) denoisers enable fast spatial restoration without deep networks, but per-frame independent inference introduces temporal flicker in video. We present TC-LUT, a training-free temporal consistency wrapper that denoises each frame with a pluggable spatial 4D LUT and fuses it with a motion-compensated previous output using SAD-based confidence. Measured on an Allwinner A133 SoC with four Cortex-A53 cores and no NPU, the locked latency-oriented preset --realtime processes 480x270 video at about 81-82 ms per frame under additive Gaussian noise with sigma=25, that is about 12 fps rather than 30 fps interactive realtime. Unlike naive unaligned blending, which lowers flicker through ghosting but hurts PSNR under motion, TC-LUT keeps PSNR from dropping and reduces temporal MAD from about 11.2 to 8.8, a gain of about 21%. PSNR rises by 0.5-0.75 dB at sigma=25 and 50 and SSIM by about 0.10, while a slight dip of about 0.1-0.4 dB can occur only at sigma=15 with stronger motion. Ablations show that gains require both motion alignment and confidence fusion; with alpha tending to 0 the output reduces to the spatial LUT. The temporal layer shows consistent flicker reduction across Wiener, PCM-inspired and self-trained DnLUT backends, with the gain magnitude depending on the spatial backend, offering a deployable quality-speed point for file-based embedded video restoration. Keywords: video denoising; lookup table; temporal consistency; edge computing; motion estimation; embedded system

To address problems such as scattered deployment points and difficult on-site operation and maintenance of distributed photo-voltaic power stations, as well as insufficient local interaction capability of traditional STM32 bare-metal gateways, a distributed photovoltaic power station monitoring system based on embedded Linux is designed. The acquisition node takes STM32F103CBT6 as the main controller and configures AC and DC voltage and current acquisition circuits. Combined with temperature, humidity, illumination and MQ-2 smoke sensors, it realizes the collection of photovoltaic electrical parameters and smoke fault alarm of inverters. The collected data is transmitted to the gateway node through LoRa wireless communication. The gateway node adopts the I.MX6ULL embedded processor, equipped with Quectel EC20-4G module, Ethernet interface, LoRa receiving module and touch display unit. In the Linux environment, the gateway completes serial port data parsing, uploads data to the OneNET cloud platform through Ethernet or 4G module based on the MQTT protocol, and realizes real-time local touch screen display via Qt. The system supports two working modes: local on-site monitoring and remote monitoring by accessing the OneNET cloud UI through a browser. Functional and performance test results show that the system meets the acquisition accuracy re-quirements and maintains stable communication operation, which can satisfy the monitoring demands of distributed photovoltaic power stations.

针对低成本嵌入式清洁机器人中环境感知精度、控制实时性与多任务连续运行难以兼顾的问题，提出一种面向资源受限平台的异构传感器融合与任务抢占协同控制方法。以STM32F103C8T6为控制核心，构建超声波—红外双传感器协同感知模型，根据两类传感器在不同测距条件下的测量特性进行低计算量加权融合；进一步将感知结果与运动控制、清洁任务建立事件驱动关系，通过有限状态机和任务抢占—状态恢复机制，使自主避障以最高优先级打断吸尘、洗涤及紫外消杀任务，并在风险解除后恢复被中断任务的控制流程，形成“感知—判决—抢占—恢复”闭环控制。搭建嵌入式清洁机器人实验平台，在10 cm到50 cm范围内开展测距及功能测试。结果表明，超声波、红外及融合测距平均绝对误差分别为1.9、2.3和1.8 cm；自主避障平均距离为15.4 cm；5次功能测试均能够按照预设控制流程完成吸尘、洗涤和紫外消杀任务。研究表明，该方法无需复杂感知硬件即可实现环境感知、风险响应与多任务协同，为资源受限嵌入式移动机器人控制系统设计提供了一种轻量化实现路径。

To address the throughput limitations of pure software architectures in high-resolution video scaling, as well as the real-time deployment challenges of low-end FPGAs under the dual constraints of resources and bandwidth, this paper designs and implements a software-hardware co-designed real-time video accelerator that achieves a three-dimensional trade-off among resource utilization, latency, and image quality while guaranteeing real-time performance. First, at the system architecture level, a streaming acceleration architecture with low-resolution storage and on-chip real-time high-resolution reconstruction is constructed, where 3-line BRAM rotational buffering and a single-clock-domain pipeline are used to process pixels in a streaming manner, so that the off-chip DDR only buffers 720p source frames, thereby reducing the external memory access bandwidth requirement. Second, on the operator-mapping level, a fixed-point-domain single-point rounding compensation is adopted to eliminate the systematic grayscale bias caused by the accumulated truncation during the shift-based normalization in 8-bit fixed-point processing. Finally, system-level verification is carried out on a Zynq-7010 SoC. In real-time 720p-to-1080p upsampling, the hardware acceleration core occupies only about 1288 LUTs, achieves a 20.27 times speedup in single-frame processing over the ARM processor, and delivers an output PSNR of 40.02 dB. With low logic overhead, the proposed method reconciles low latency with image quality, providing a reusable design paradigm for the hardware mapping and engineering deployment of image algorithms on low-end FPGAs.

Analog circuit sizing involves high-dimensional design spaces, costly simulations, and limited samples, which often reduce Bayesian optimization efficiency. A Bayesian optimization algorithm with dynamically fused acquisition functions is proposed. Latin hypercube sampling is used for initialization, while truncated Gaussian subspace sampling generates candidate points. The search center, step size, and covariance structure are updated from previous evaluations. For local Gaussian-process modeling, hyperparameter priors are introduced to form a maximum a posteriori objective, solved by multi-start L-BFGS to reduce sensitivity to initialization and local optima. During candidate selection, sigmoid weights dynamically combine upper confidence bound and expected improvement ac-cording to simulation progress, allowing the search to shift gradually from global exploration to local exploitation. Tests on three practical analog circuits show that, compared with tSS-BO, the proposed algorithm obtains up to 1.46 times as many feasible designs and improves the optimization objective by up to 19.95%, with efficient and stable convergence under limited simulation budgets.

To address the potential performance degradation caused by signal saturation in the signal chain of RF transceivers during practical operation, this work presents an on-chip saturation detection circuit that can be integrated into RF transceivers. The proposed saturation detection circuit mainly consists of an energy detection circuit based on an operational amplifier, a reference voltage generation circuit, and a static hysteresis comparator. Targeted optimizations are implemented to achieve low power consumption and a compact circuit area. Specifically, the energy detection circuit employs an operational amplifier with a low gain-bandwidth product (GBW) to realize the filtering function, thereby eliminating the need for an additional low-pass filter and significantly reducing the area overhead. In the reference voltage generation circuit, a dual-range temperature-code multiplexing scheme is adopted to reduce the hardware overhead of the decoder, thereby further reducing both the circuit area and power consumption. The proposed circuit is designed and fabricated in a 40-nm CMOS process. The carrier frequency is 800 kHz, and the detection speed reaches 80 kHz. The fabricated circuit occupies an area of only 30 μm × 160 μm, with a power consumption of 42.9 μW.

为了解决集成电路制造中ICP、CCP刻蚀工艺存在的缺陷预警滞后、过程控制精度不够等问题，提出了一种基于故障检测与分类（FDC）、先进制造系统（AMS）和设备控制与监控系统（ECMS）三层协同的刻蚀工艺缺陷预警和过程控制方法。首先对ICP和CCP刻蚀工艺的物理机理以及常见的缺陷原因进行了分析，建立了一个基于多变量统计过程控制的FDC实时预警模型，用Hotelling T²统计量和平方预测误差（SPE）联合判别来检测工艺异常；其次建立了AMS虚拟量测模型，用深度神经网络实现刻蚀关键尺寸的实时预测，把量测周期从离线测量的4～6小时缩短到在线预测的秒级响应；再次设计了ECMS设备状态监控和预测性维护框架，用传感器数据融合来完成设备健康度的评价；最后提出三层协同管控架构，依靠数据融合和信息闭环达成缺陷预警、过程改善、设备调控的闭环控制。实验结果表明，采用本方法的刻蚀缺陷预警准确率为96.3%，误报率为2.1%，刻蚀均匀性偏差控制在±1.8%以内，刻蚀选择比提高到35：1，晶圆良率提高3.2个百分点。该方法给集成电路制造刻蚀工艺的智能化控制提供了一条有效的技术途径。

To improve the informatization level of safe operation and remote maintenance for large steel silo in coal-fired power plants, a multi-source sensing fusion health-state assessment method based on nonlinear spatial weighting of silo-wall strain is proposed, and an edge-cloud-Web collaborative monitoring system is developed. The edge acquisition terminal uses an STM32F407 controller and accesses multiple demodulators through Modbus to acquire strain, temperature and humidity, inclination, and settlement data. A three-dimensional radar scanning robot is used to obtain material-surface point clouds, material level, and level-difference information. After edge parsing and classified encapsulation, monitoring data are transmitted to the cloud through 4G. The cloud mainly performs terminal connection management, data parsing and storage, control-command forwarding, and health-state assessment. The Web application provides real-time monitoring, historical query, abnormal alarms, remote control, and visual presentation of the silo health state. Field tests show that modules can operate collaboratively and realize an application loop integrating field sensing, remote monitoring, and health assessment.

Aiming at the problems of linear resource growth and difficult timing closure when an FPGA receives multi-node RapidIO messages on aerospace TT&C heterogeneous platforms, a fixed-channel multiplexing mechanism based on message ID preprocessing and dynamic release is proposed. The design establishes a closed-loop architecture of “preprocessing–parallel processing–resource release” to achieve time-division multiplexing of multi-node messages and automatic recycling of channel resources. Experimental results demonstrate that, compared with traditional resource stacking schemes, the proposed method maintains constant FPGA resource consumption (LUT/BRAM) while supporting massive node access. It significantly optimizes timing closure performance and reduces compilation cycles. The scheme has been validated through its application in multiple domestic aerospace integrated engineering projects.

For the 14nm FinFET advanced process node, traditional BSIM physical models have long calibration cycles and poor adaptability to new devices, lookup table models have insufficient accuracy, and machine learning device models are difficult to access commercial EDA simulation tools. This paper proposes a complete two-layer collaborative DTCO optimization process of ANN device proxy + random forest circuit proxy. First, a fully connected artificial neural network with batch normalization and LeakyReLU activation is built based on the Sentaurus TCAD multi-dimensional simulation dataset, integrating gate structure parameters, aging stress, and electrical bias inputs to accurately predict FinFET leakage current and terminal charges. An automated parsing and conversion tool is designed to export the trained PyTorch network into a Verilog-A device model compatible with Spectre/HSPICE, connecting the machine learning model with the SPICE simulation link. Latin hypercube sampling is used to traverse the high-dimensional design space of device-circuit coupling, and after batch simulation, a random forest lightweight circuit proxy model is trained to replace time-consuming repeated circuit simulations. Based on the NSGA-III multi-objective evolutionary algorithm, the Pareto optimal solution set is solved with the full-adder unit delay and power consumption as optimization objectives. Experimental results show that the test set determination coefficient of the FinFET device ANN model is R2=0.996, which is 105 times faster than the native TCAD simulation; the overall acceleration of the hierarchical proxy model collaborative optimization process is 30 times; the optimized design can achieve a 22% reduction in delay under the same power consumption and a 31% reduction in power consumption under the same delay. The proposed process can fully realize cross-layer joint optimization of device-process-circuit including reliability aging variables, providing a standardized technical solution for the automated implementation of advanced process DTCO automation.

To address the frequency-dependent rank growth and the resulting loss of compression efficiency when adaptive cross approximation (ACA) is directly applied to the loop-impedance matrix in broadband magneto-quasi-static resistance and inductance (RL) extraction, a basis-transformation-based ACA scheme is proposed. The directional degrees of freedom of vector current basis functions are isolated into three sparse mapping matrices, leaving a dense core matrix that contains only scalar couplings between panels. ACA is then applied exclusively to this core matrix. The formulation is combined with mixed surface meshes, loop-current analysis, and a broadband equivalent surface-impedance model. Numerical results show that the rank and compression ratio of far-field blocks remain nearly frequency independent. For the two-conductor example, the maximum speedups of matrix filling and compression are approximately 6 and 80, respectively. For the FCBGA and FCCSP examples, matrix-generation time is reduced from 89 s to 13 s and from 304 s to 25 s, while peak memory is reduced by 20.8% and 31.3%. The maximum reported deviations of the extracted R and L parameters are 4.6% and 1.73%, respectively.

To meet the demands of humanoid robot joint actuation for high power density, high efficiency, fast response, and high reliability, this paper systematically reviews the key technologies and development trends of motor gate driver ICs. It first analyzes the differentiated requirements of various joints in terms of power, voltage, and control performance, and compares the technical characteristics of silicon-based and GaN power devices. Then, focusing on four major trade-offs—switching speed versus electromagnetic interference, dead-time optimization, signal transmission rate versus common-mode transient immunity, and power density versus thermal integration—it surveys promising technologies including active gate driving, dead-time optimization, high-reliability signal transmission, monolithic integration, and intelligent sensing. Finally, it summarizes the technology roadmaps for different joint types and points out that high-frequency operation, integration, intelligence, and specialization will be the future development directions.

A wide-dynamic-range reconfigurable logarithmic amplifier based on 0.18 μm CMOS process is designed to address the problems of wide bandwidth of partial discharge signals of electrical equipment and significant amplitude difference in sensor output signals. To balance broadband response and wide dynamic range detection capability, a successive detection logarithmic amplification architecture is adopted, which combines multi-stage limiting amplification with full-wave detection circuits to realize logarithmic compression of input signals. To improve bias stability and reduce the influences of process and temperature variations, a constant-transconductance self-bias circuit is introduced to enhance the consistency of bias current and static operating point of each limiting amplification unit. Aiming at the differentiated requirements of logarithmic slopes in different detection scenarios, a logarithmic response slope reconfiguration method based on an on-chip digital switch array is proposed. With the main circuit structure unchanged, flexible configuration of multiple logarithmic response slopes is realized by selecting outputs of different detection current branches through the digital switch array. Simulation results show that the designed amplifier achieves a −3 dB bandwidth of 40 MHz and an effective input dynamic range of 72 dB under a 2 V supply voltage, with the logarithmic conformity error within ±1.9 dB and eight adjustable slope gears supported. Integrating broadband performance, wide dynamic range and reconfigurable characteristics, the proposed amplifier can meet the application requirements of partial discharge online monitoring systems for multi-sensor adaptation, wide-dynamic-range detection and multi-gear output configuration.

大语言模型（Large Language Models，LLMs）的快速发展，为硬件/软件协同设计中的代码自动生成带来了新的可能。本文提出一种面向多处理器片上系统（MPSoC）平台的AMBA3-AXI互连代码生成混合框架，将基于模板的确定性生成方法与提示工程相结合。该框架由参数列表生成器、模板化代码生成器和LLM驱动的智能代码生成器三部分组成，在保持代码结构可预测性的同时，提升了对动态设计需求的适应能力。基于Specman + eVC验证环境的综合评估表明，该框架能够提升可扩展性、减少人工工作量并提高代码正确性。实验结果进一步证明，引入LLM有助于改善代码可维护性、增强协议一致性，并缩短MPSoC设计与验证周期。

To address the engineering challenges of fragmented toolchains and inefficient data flow in semiconductor device modeling and Design Technology Co-Optimization (DTCO) workflows, this paper presents the design and implementation of SCNN (Smartchip Neural Network), an integrated software platform. By leveraging established machine learning and multi-objective optimization algorithms, SCNN adopts a hierarchical modeling strategy to construct an automated DTCO workflow spanning from device-level data processing to circuit-level design space exploration. The platform integrates 13 machine learning algorithms and 25 multi-objective evolutionary algorithms, supporting six core functions: device simulation, data processing, device predictive model training, Verilog-A compatible neural network model export, circuit predictive model training, and multi-objective optimization. In MOSFET DC characteristic modeling experiments, the algorithms integrated within SCNN consistently achieve a coefficient of determination R² > 0.995 fitting accuracy. The platform enables automated conversion of trained neural networks into Verilog-A compatible models, which are suitable for DC operating point analysis and low-frequency AC simulation scenarios. A multi-objective optimization case study of an operational amplifier demonstrates the effectiveness of the hierarchical modeling strategy for efficient circuit design space exploration. The platform has been validated in multiple industrial projects.

Existing DDS waveform generators cannot simultaneously suppress phase noise and spurs, failing to balance time- and frequency-domain performance of arbitrary waveforms. This paper builds an FPGA+AD9910 waveform generation system. Isolated LDO power supplies and low-jitter clocks suppress noise at source; the mechanisms of spurs and phase noise are analyzed with a spectral error model built. A 10 MHz 7th-order Bessel low-pass filter is designed to suppress spurs and output distortion-free waveforms.Simulations and measurements show the filter’s passband group delay ripple <1% and 125 dB stopband attenuation at 50 MHz. The system achieves 50.57 dB spurious rejection, one-order lower THD for arbitrary waveforms, and 33 dB phase noise improvement at 100 Hz offset of a 100 MHz carrier, satisfying radar and precision test demands.

To address the issue that traditional bandgap reference circuits tend to introduce additional power consumption when reducing temperature drift, a low-power and low-temperature drift bandgap reference source with nA-level static current has been designed. This circuit employs a clamp structure without the traditional bias branch to generate PTAT current, avoiding the additional bias current caused by traditional operational amplifier clamping; at the same time, a segmented curvature compensation module based on the low bias transconductance comparison branch is introduced to generate compensation currents in the low-temperature and high-temperature sections respectively, in order to suppress the high-order temperature curvature in the first-order compensated reference voltage. The key MOS transistors in the compensation branch operate in the sub-threshold region, and the exponential characteristic of sub-threshold current is utilized to achieve low-power temperature compensation. Additionally, a transistor collector-to-substrate leakage current compensation circuit is introduced to reduce the influence of high-temperature leakage current on the reference output voltage. Simulation results show that at a 3.3 V power supply voltage and within the temperature range of -40 to 125 ℃, the bandgap reference output voltage is 1.209 V, the temperature coefficient is 2.33 ppm/℃, the low-frequency power supply rejection ratio is 64 dB, the static current is 365 nA, and the corresponding static power consumption is approximately 1.20 μW.

Angular encoder chips often operate in complex environments and impose strict requirements on signal filtering. However, constrained by limited on-chip space, integrating complex filtering circuits remains a significant challenge. To address this issue, this article proposes a folded Kalman filter circuit that can co-optimize area and latency. The design employs four optimization strategies—a folded architecture, filter model splitting, Kalman parameter pruning, and operation sequence reordering—which significantly reduce hardware overhead. Processing a single-channel signal requires only 2 adders, 1 multiplier, and 1 divider. Implemented in 180nm process node at a 50MHz clock frequency, the circuit supports high-speed signal processing with a sampling rate of up to 2MSPS, achieving high-frequency noise attenuation up to 22dB. Without compromising filtering accuracy, our design reduces DSP resource consumption by 68% and computational latency by 53% compared to related works. It can be effectively applied to miniature signal processing chips, such as angular encoders.

【目的】目前如光传输网络OTN（Optical Transmission Network）、以太网数据通信传输的研究热点都集中在高速率传输，例如40Gbps以上，相应的串行器/解串器SerDes（Serializer-Deserializer）技术和芯片也随之推出，这些高速SerDes都存在下限速率，目前SerDes芯片存在速率下限，通常在500Mbps左右，因此500Mbps以下的数据串行传输不能直接使用SerDes，为了解决此问题，本文深入分析了过采样与SerDes结合的数据传输，并重点研究了接收端的过采样数据恢复。【方法】本文给出了基于SerDes的时域过采样设计，并详细设计了接收端的过采样数据恢复模块，给出了设计接口和信号说明；针对发送端、接收端的时钟频差时的过采样给出了详细分析和采样补偿或者舍弃，而且讨论了长连1或者长连0的最大容许长度，以便选择何种物理层编码码型。最后，对两种频差情况进行了详细仿真和讨论，并且基于紫光国产FPGA芯片PG2T100的板卡开展了测试验证。【结果】仿真和测试结果表明，基于SerDes的时域过采样设计系统满足500Mbps以下的数据传输需求。【结论】基于SerDes的时域过采样系统设计详细、仿真全面、上板测试充分，为500Mbps以下的数据串行传输提供了工程设计指导。