This paper describes a LDO with low 1/f noise and wide bandwidth. With the help of chopping technology, the achievable output noise of LDO is 139nv/√Hz at 10Hz, 64.7nv/√Hz at 100Hz, and 36.3nv/√Hz at 1kHz under the worst corner. Since the 1/f noise corner is as low as Hertz level, it can be used to power the modules whose signal bandwidth is Hertz level. The LDO proposed in this paper also adds the current fast compensation mechanism (CFA) and the fast compensation current mechanism at the load end of the output regulator, which can not only achieve a very high SNR, but also improve the power supply suppression energy and fast power supply capacity. The CFA also splits the low frequency pole between the amplifier and the PMOS regulator into two higher frequency poles, which extends the LDO bandwidth and achieves a higher PSRR.

In response to the problems of delayed response in elderly care at home and in the community, inconvenient positioning, inability to call for help in case of sudden illness, and easy getting lost, this paper designs an intelligent monitoring system suitable for the elderly. The system takes the STC12C5A60S2 single-chip microcomputer as the core, integrates the PulseSensor heart rate sensor, DS18B20 temperature sensor, GT-U7 GPS module and buzzer, and adopts the "hardware integration + software control" mode. Data transmission is achieved through single-wire and serial communication without the need for additional conversion modules, simplifying the hardware design. The system can accurately monitor the physiological parameters of the elderly such as heart rate and body temperature, output real-time positioning information, and automatically trigger an alarm in case of abnormality. It operates stably and is easy to operate. This system effectively compensates for the shortcomings of traditional monitoring, can comprehensively ensure the safety of the elderly, and has controllable costs and strong practicality. It is suitable for home and community elderly care scenarios and can meet the daily monitoring needs of the elderly, with high promotion value and application prospects.

In order to improving the storage efficiency of NVMe SSD in airborne embedded storage system under complex task scenarios and ensuring the operational stability and accuracy of the embedded storage system, this paper does some research on reading-writing architecture of NVMe SSD based on synchronous multi-channel technology. By elaborating the design methods of I/O queues, physical region pages and interrupt processing under the synchronous multi-channel architecture, the implementation process and operating characteristics of the synchronous multi-channel NVMe SSD read-write architecture are intuitively presented. Meanwhile, a real test scenario is constructed based on a multi-core processor platform and deployed in an actual airborne embedded storage system. The experimental results verify the correctness of the proposed synchronous multi-channel NVMe SSD read-write architecture.

In power converters, extended soft-start duration and loop compensation typically require large capacitors. However, off-chip capacitors increase packaging cost and peripheral complexity, reducing system reliability. Although on-chip integration is viable, capacitance density is strictly limited by process constraints and chip area, thereby restricting compensation network flexibility and soft-start time adjustment. To address these limitations, a highly integrated DC-DC converter with a simplified off-chip environment is proposed. For internal loop compensation, an improved scheme employing a transconductance amplifier achieves equivalent capacitance amplification, enhancing stability and design flexibility. For on-chip soft-start, a capacitor-free method utilizing charging current diversion is presented, enabling prolonged soft-start time within a limited area to suppress inrush current effectively. The converter is implemented in a 0.18-µm BCD process with an area of 1.73 mm². Measurement results demonstrate that, at a 5 V/2 A output rating, the converter achieves an efficiency exceeding 80% over a load range of 1 mA to 2 A, with a peak efficiency of 95.1%. Under a load step change, the output voltage overshoot and undershoot are less than 180 mV, and the recovery time is approximately 200 μs, indicating good stability of the converter. The measured start up time is approximately 4.8 ms.

At the 180 nm CMOS process node, multi-objective optimization of standard-cell libraries still relies heavily on SPICE simulation, resulting in severe computational bottlenecks. A single transient analysis typically takes ~100 ms; a typical library optimization requiring over 10 000 iterations consumes approximately 2.1 minutes even with 8-core parallelization. This paper proposes a lightweight surrogate modeling framework that constructs a hybrid dataset of only 155 samples by fusing 25 high-fidelity PySpice simulations (GF180MCU PDK) with 130 open-source benchmark points. After systematically comparing eight machine-learning architectures, the multi-layer perceptron (MLP) model achieves the best accuracy-speed trade-off (R² = 0.8734 for power and 0.9521 for delay) with an inference time of only 1μs, delivering approximately 1 00 000× acceleration over conventional SPICE. Zero-shot cross-cell generalization yields an average R² of 0.6746; fine-tuning with merely 15 additional SPICE samples per new cell further improves performance. Industrial ROI analysis for a 50-engineer design team shows the design cycle reduced from 2.1 min to 0.5 min, with a 3-year net benefit yielding ROI of 200–300 %. The proposed approach provides a deployable, cost-effective solution for AI-assisted circuit design automation with substantial engineering and economic value.

Targeting the characteristics of GJB/Z 299C-2006 "Reliability Prediction Handbook for Electronic Equipment," where predicted reliability data for various components, including integrated circuit chips under operational conditions, often deviate significantly from actual situations, a failure mechanism-based reliability data validation method has been designed. This validation method starts from the failure mechanisms in very large-scale integrated circuit chips and, based on an analysis of domestic and international standards for evaluating reliability related to failure mechanisms, summarizes the failure physics models in national standards. Leveraging reliability test structures, through accelerated life testing for single failure mechanisms, the median time to failure for primary failure mechanisms is derived. By converting the median time to failure into failure rates, reliability data for very large-scale integrated circuits is obtained, ensuring the validity of the reliability data from a physical mechanism. These reliability data can be applied to the reliable utilization of avionics products while also supporting reliability prediction work for electronic products.

Network-on-Chip (NoC) has been widely adopted for on-chip communication due to its advantages of high integration, strong scalability, and low power consumption. This paper designs and implements a highly reliable dual-layer Network-on-Chip circuit. A redundant architecture is adopted via two NoC layers: one layer is used for normal data transmission, while the other layer is dedicated to timeout retransmission. To enhance anti-interference capability, triple modular redundancy (TMR) is applied to key routing control information of event packets, including flit type coding, destination router node information, and NoC ID. Meanwhile, parity check is used for the carried address and data information to ensure the correctness of data transmission. Simulation results verify that the proposed highly reliable dual-layer NoC circuit achieves correct functional behavior and excellent fault-tolerant performance.

With the widespread application of FPGAs in high-performance embedded computing and data centers, the demand for data transmission bandwidth via the PCIe interface is increasing. Xilinx's XDMA IP core, as a mainstream high-performance DMA solution, often has its actual performance limited by the complex memory management mechanism of the Linux system. This paper studies the key points affecting the XDMA transmission performance in the standard Linux driver model through theoretical and modeling analysis, and finds that the "lazy allocation" strategy of user-space memory causes the allocation and mapping of physical pages to be delayed until after the DMA transmission request is initiated, frequently triggering page faults and increasing the TLB miss rate, which seriously restricts the efficiency and determinacy of high-bandwidth transmission. This paper proposes an application layer memory pre-mapping optimization strategy that utilizes advanced parameters of the mmap system call. This strategy moves the physical memory allocation, page table establishment, and page locking operations forward to the system initialization stage, thereby reducing the runtime overhead and significantly improving the subsequent memory access efficiency. Theoretical analysis and experimental results show that this strategy increases the data transmission rate by 85.5% under the default TLB size compared to the optimized version. Furthermore, the impact of TLB size on XDMA transmission is studied, which is of great reference significance for building high-performance, low-latency embedded heterogeneous systems.

Time sensitive network has the characteristics of low latency, low cost, and high reliability. The Time-Aware Shaper (TAS), defined by the IEEE 802.1Qbv standard, stands as one of the critical technologies for enabling deterministic network traffic and holds a core position within the TSN protocol suite. First, by means of logical designs such as top-level architecture, workflow, and active-standby coordination, a method for implementing TAS is proposed. Second, by constructing constraints for traffic with different priorities, a deterministic scenario is designed to verify the implementation of clock synchronization and the time-aware shaper. Finally, through comparative experiments conducted before and after enabling TAS, the superiority of TSN technology over standard Ethernet in terms of low latency and low jitter is validated. The results show that, after enabling clock synchronization and gate control functions, the average delay and jitter are only about 1/20 to 1/15 of the original, which is significantly different. This provides a demonstration solution for the rapid promotion of TSN technology.

Addressing the power supply issues of noise-sensitive electronic devices such as mobile phone cameras and Bluetooth, a low dropout regulator (LDO) with high power supply rejection ratio (PSRR) and ultra-low dropout voltage has been designed. The circuit employs an N-type field-effect transistor (NMOS) as the regulation transistor and is powered by a dual-power supply. It segregates the bias power supply from the input power supply of the regulation transistor, thereby attaining a high Power Supply Rejection Ratio (PSRR) and an ultra-low dropout voltage. The design incorporates a pre-regulation modulation circuit and a low-pass filter to process the reference voltage, enhancing the PSRR of the bias power supply. The main loop adjust the system's pole-zero distribution through inverse nested Miller compensation, improving the overall PSRR of the circuit. The circuit and layout design were completed based on a 0.18µm CMOS process. The maximum load current of the circuit is 500mA. Simulation results show that the dropout voltage at maximum load current is 100mV. At a load of 10mA, the power supply rejection ratio (PSRR) of the input power supply at frequencies of 100Hz, 1kHz, 10kHz, and 1MHz are -110dB, -90dB, -70dB, and -65dB, respectively.

Spiking neural networks (SNNs) represent and process information using discrete spike trains, exhibiting event-driven and sparse computation characteristics and offering strong potential for energy-efficient intelligent computing. To fully exploit their low-power advantages, dedicated hardware implementation techniques and neuromorphic chips for SNNs are of significant research importance. From the perspective of hardware implementation, this paper systematically reviews the full hardware development chain of SNNs, covering neuron models, information encoding methods, network structures, and hardware architectures. The paper describes commonly used spiking neuron models and information encoding methods, discusses network structures including fully connected, convolutional, and attention-based architectures, systematically summarizes research on hardware architectures, compares the advantages and limitations of different circuit implementation technologies and computing paradigms, and analyzes current key challenges while outlining future research directions.

RT-Thread is an open-source embedded Real-Time Operating System (RTOS) that has been widely adopted in the Internet of Things (IoT) domain due to its rich components and excellent tailorability. TH4001 is a 32-bit Reduced Instruction Set Computer-V (RISC-V) processor chip targeted at lightweight embedded control scenarios. It suffers from limited on-chip Static Random Access Memory (SRAM) capacity and is not equipped with standard hardware peripherals such as the Universal Asynchronous Receiver/Transmitter (UART). To date, no mature solution exists for porting the RT-Thread operating system to the TH4001 platform. To fill this gap, this paper presents a complete RT-Thread porting scheme for the TH4001 chip, focusing on addressing the constraints of insufficient SRAM capacity and the lack of UART peripherals. The scheme adopts a hybrid loading and running architecture for system booting, and leverages the Programmable I/O (PIO) module to emulate a UART interface for console output. Experimental results demonstrate that the ported RT-Thread system boots successfully, runs the user main thread, and correctly performs context switching. This work serves as a reference solution for porting RTOS to similarly resource-constrained RISC-V chips.

Aiming at the problems of redundant volume, large link loss, and weak anti-electromagnetic interference of traditional FMCW radar transceiver systems in miniaturized devices, this paper designs and implements a highly integrated FMCW radar transceiver SiP module operating in the 4200-4400MHz frequency band, which is suitable for aircraft altimeters. Based on System-in-Package (SiP) technology, the module adopts a 4-layer BT substrate to realize heterogeneous integration of multiple chips. It internally integrates a transmission link, a reception link, and a clock generator. A DDS is used to generate 500MHz~700MHz signals, which are then upconverted to the target frequency band in one step. The module features transmit power control, receive gain adjustment, and frequency-swept waveform configuration. The system is designed with a transmit output power of 20dBm, a maximum receive link gain of 80.5dB, and a transmit-receive isolation of ≥90dB, with a compact package size of only 14mm×14mm. Test results show that the module has a transmit power flatness of less than 1dB, a noise figure of only 4.08dB at maximum gain, and an FMCW signal linearity of 0.012%. It can achieve kilometer-level altitude detection and fully meets the application requirements of aircraft for miniaturization, low power consumption, and high signal stability.

QuestaSIM/ModelSIM serves as a prevalent simulation platform for FPGA verification, where workflow automation has demonstrated substantial efficacy in enhancing verification productivity. The canonical simulation flow of QuestaSim/ModelSim comprises six sequential stages: compilation, optimization, design elaboration and loading into the VSIM kernel, execution and debugging, context preservation, and platform termination. Contemporary automation scripts predominantly leverage primitive commands documented in the QuestaSim/ModelSim Command Reference Manual to mechanize this pipeline in a batch-processing manner. Switching between different testcases under the existing simulation workflow script necessitates exiting the QuestaSim/ModelSim platform, modifying the script to select the target testcase, and then repeating the entire workflow. Executing a large number of testcases necessitates frequent launches and exits of the simulation platform. Moreover, the current workflow lacks a dedicated error-handling procedure for common simulation-time errors. To address these issues, this paper proposes an interactive, automated simulation workflow implemented in Tcl/Tk. The workflow features GUI-based testcase selection and comprehensive error handling. Experimental results show that it enables seamless testcase switching without exiting the simulation platform and provides handling for common errors, significantly reducing manual steps. This work advances automation in multi-testcase scenarios and offers a practical path toward improving simulation automation in FPGA software verification.

The steady-state simulation of analog integrated circuits generally adopts the traditional transient analysis method. Therefore, it is necessary to integrate from the initial state to the steady state over a long period of time. For high-Q and low-damping circuits (such as LC oscillators), the solution process is thus time-consuming and becomes a significant bottleneck in design efficiency. This paper proposes an efficient steady-state simulation method based on the Shooting method, converting the periodic steady-state solution into a boundary value problem. Firstly, the state transition function is constructed, and then the Newton-Raphson iterative method is used to solve it. At the same time, pseudo-transient initialization and adaptive damping strategies are combined to ensure rapid and reliable convergence. What's more remarkable is that the simulation environment is built based on the PyTorch framework, using automatic differentiation to directly and accurately calculate the Jacobian matrix, and supporting dual acceleration on CPU and GPU. Through experimental verification of three types of circuits: ring oscillators, LC voltage-controlled oscillators, and Gilbert mixer, it is clearly and rigorously proved that the proposed method, while ensuring accuracy, increases the simulation speed by 20 to 117 times compared to traditional methods. It has extremely prominent acceleration effects for high-Q circuits and demonstrates its superiority in steady-state simulation of analog integrated circuits.

This work presents the design and implementation of a distributed gallium arsenide power amplifier (DPA) with integrated temperature and power sensing for high-power ultra-wideband applications, based on a 0.15-μm GaAs pHEMT process. The proposed amplifier consists of a distributed power amplifier (DPA), a temperature sensing unit, and a differential power detection unit. The distributed power amplifier adopts a cascode architecture, which significantly enhances the output power. The proposed temperature sensing unit employs a multi-point array-based temperature measurement scheme, in which different temperature sensing nodes can be selected through an external encoder. The differential power detection unit outputs detection voltages through the Vdet and Vref pins, effectively suppressing the influence of temperature variations on power detection accuracy. Measurement results indicate that, under the operating condition of Vgs = −0.5 V, the DPA achieves an operating bandwidth from DC to 28 GHz, with the output power (Pdc) increased to 30 dBm, a power-added efficiency (PAE) of 15%, and a gain flatness better than ±1 dB. Small-signal measurement results demonstrate that, over the operating bandwidth, both the input return loss (S11) and output return loss (S22) are better than −10 dB. The overall chip layout area is 3.8 mm × 1.5 mm.

Aiming at the problem that the existing FPGA matrix inversion methods are difficult to balance hardware resources, calculation delay and calculation accuracy, this paper proposes a matrix inversion architecture that integrates algorithm optimization and hardware architecture design. In this paper, based on MGS-QR decomposition, the parallel vector operations in the operation flow are integrated, and the calculation of the inverse matrix is transformed into the integration of the partial sum of each iteration in the iterative process, and the vector processing unit adaptation algorithm supporting multiple vector operation modes is designed. This architecture enables the inversion of an N×N real matrix to be accomplished using resources that grow quadratically with the matrix size and clock cycles that increase linearly with the matrix size. It is capable of adapting to the processing requirements of matrices of different sizes. Compared with the traditional MGS-QR factorization matrix inversion method, the designed architecture further reduces the amount of DSP usage and significantly shorts the calculation delay under the premise of ensuring the same calculation accuracy, which can provide an efficient and highly reliable engineering solution for real-time matrix inversion in embedded systems.

In low-voltage distribution networks, the power communication module is responsible not only for high-speed communication but also plays a crucial role in feeder identification and phase identification. The zero-crossing detection function of the module is key to achieving feeder and phase identification. The intelligent verification of zero-crossing detection circuits is a challenging aspect in power distribution technology. Traditional centralized zero-crossing detection verification systems suffer from high latency, network dependency, high costs, poor maintainability, and low data security. To address these issues, this paper proposes the design and application of a high-speed power communication module zero-crossing detection verification system tailored for edge computing. The system is designed for edge computing and consists of five layers: hardware device layer, communication interface layer, communication protocol layer, business logic layer, and application software layer. In the zero-crossing detection verification algorithm, the focus is on ensuring networking, data reading, and error calculation processes to ultimately achieve edge-parallel computing, data storage, and conclusion output. Currently, the average mean time between failures for edge computing-oriented zero-crossing detection verification systems reaches 264 hours, with an average test duration of 5.1 seconds and a verification accuracy rate of 99.96%. Compared to traditional methods, costs are reduced by 48%. The system has now been widely deployed in manufacturing factories for zero-crossing detection verification, achieving significant economic benefits and providing new insights for the application of edge computing technology in power systems.

Aiming at the technical bottlenecks of limited functionality and inadequate measurement precision inherent in conventional current data sampling modules, this study develops a high-precision current data acquisition module based on STM32 series microcontrollers. The module integrates a high-performance analog-to-digital (AD) conversion chip and a network communication interface, thereby enabling high-precision sampling of current signals and real-time data transmission. Field test results indicate that the proposed current data acquisition module exhibits stable operation and high data accuracy. It can fully meet the application requirements of multi-point current monitoring in industrial workshops, and thus boasts considerable potential for engineering popularization and remarkable practical significance.

In real-time embedded bare-metal systems such as relay protection devices, traditional synchronous logging schemes suffer from high interrupt response latency, poor thread safety, and significant resource consumption. This paper proposes a lightweight asynchronous logging scheme tailored for bare-metal systems. The scheme adopts a dual-buffer asynchronous write mechanism: only raw parameter values are saved in interrupt service routines, while log formatting and storage operations are completed in the background main loop. Critical section protection is achieved through interrupt disabling, ensuring thread safety in interrupt nesting environments. A unified storage strategy is designed for both AMP architecture and single-core bare-metal scenarios, supporting log level filtering, Hexdump memory dumping, and power-fail safe storage. Experimental results on the RockChip 4-core processor show that the scheme reduces single log recording time to within 1.1μs, achieving a 6x performance improvement compared to standard formatting printing interfaces, with peak buffer occupancy of 65%. The dual-buffer design and flow control mechanism effectively guarantee high real-time performance and reliability of the system.This solution is suitable for embedded bare-metal systems in fields such as relay protection, industrial control, and aerospace, where real-time performance and reliability are of the utmost importance.