The existing debugging functionalities in embedded real-time operating system application development encompass variable inspection,breakpoint management,and memory read/write operations,which generally satisfy users’ debugging requirements for multitasking applications.However,there is limited focus on debugging specific tasks during the multitasking debugging process.Particularly,when multiple tasks invoke the same funtion ,it creates inconvenience for users during debugging.This paper presents a method for debugging specified tasks in multitasking programs,implemented on an embedded real-time operating system and an autonomous debugger software for the “HunXin” digital signal processor. This approach significantly enhances the efficiency of multitasking application debugging and reduces the application development time.

PCIe interface bus enables low-latency, high-bandwidth data transmission between CPU and FPGA, with the key factor being the design of a DMA engine, allowing CPU to be uninvolved in the data transmission. However, the majority of current CPU+FPGA data transmission solutions are based on foreign FPGA devices from Xilinx, and there is a severe shortage of commercial IP cores for domestic FPGA, making it challenging to port these solutions to domestic FPGA platforms. Therefore, this paper uses domestic FPGA to design a PCIe interface-based DMA engine and its corresponding driver, hiding the parsing of transaction layer packets in the PCIe protocol stack and reducing the development complexity of domestic FPGA in PCIe based applications. Experimental results demonstrate that, the DMA engine achieves a read throughput of 784 MB/s and a write throughput of 800 MB/s via PCIe 2.0 x2 bus, reaching 82% and 84% of the theoretical maximum bandwidth of PCIe 2.0 x2, respectively.

该文针对微小型无人机实时车辆检测中的体积、能效及复杂背景问题，提出一种基于FPGA的位置加权梯度直方图（PWGH）与支持向量机（SVM）的低成本方案，将传统HOG的9bin扩展为9×2复合直方图，提升特征区分度，在UAV_ROD数据集上准确率提高8.4%，在Zynq7020硬件平台实现50帧/秒处理速度，功耗仅2.3W，验证了该方案在精度、速度、低功耗及小型化上的优势，具有一定的工程应用价值。

This study proposes a design method for a multi-channel DMA controller based on the AMBA AHB bus protocol. It puts forward a relatively complete design scheme for the multi-channel DMA controller, and provides detailed module designs.Through the multi-channel design, channel arbitration enables the two channels with the highest priority to alternately read and write, avoiding the problem that other channels cannot transfer data for a long time due to the excessively long transmission time of a single channel. And resource consumption is reduced through time division multiplexing. In addition, the situations that may occur in external devices are handled, which improves the transmission efficiency and reduces the amount of resource usage.

With the increasing demand for non-volatile storage in embedded systems, the functional verification of embedded flash (eFlash) controllers has become a crucial step to ensure system reliability. In response to the low efficiency and poor timing compatibility of traditional directed testing in eFlash controller verification, this paper designs and implements an efficient verification platform for eFlash controllers based on the Universal Verification Methodology (UVM) and oriented to the AHB-Lite bus. The platform utilizes the core components of UVM to achieve a hierarchical architecture, and employs automated scripts and an integrated register model (RAL), adopting random constraint testing and coverage-driven strategies. This ensures verification completeness while shortening the verification cycle. The verification results show that this verification platform can effectively verify the various functions of the eFlash controller, achieving 100% code coverage and 100% functional coverage.

针对SOC平台在机载环境中缺乏专业视频传输能力的问题，本文设计并实现基于RK3588与FPGA协同工作的机载视频处理与传输系统。系统以RK3588为核心处理单元，完成视频流的实时采集、目标检测与图像处理，并通过MIPI-DSI2接口将处理结果传输至FPGA模块。考虑到MIPI-DSI2接口不具备远距离、高干扰场景下传输能力，FPGA端引入三帧缓存机制并完成图像格式转换与SDI编码，以生成符合SMPTE标准的视频流输出，有效保障复杂机载环境下的图像传输质量与系统稳定性。

To meet the requirements of overcurrent protection for industrial equipment, a modular design-based electronic circuit solution is proposed, aiming to achieve precise current detection and rapid protection response. The modular design architecture integrates current sensing amplifier, hysteresis comparator and relay to work collaboratively: the current sensing amplifier is used to achieve signal acquisition with 0.1mA level accuracy, the hysteresis comparator is used to set the protection threshold, and the solid-state relay is used to control the circuit's on-off. Experimental results show that when the current exceeds the set threshold, the circuit completes the disconnection action within 10ms, and remains in the open state even when the threshold current drops below the threshold, avoiding false recovery. After multiple cycle tests, the protection action accuracy rate reaches 98.4%, effectively eliminating potential damage to the equipment caused by multiple overcurrents, and providing an innovative solution for high-precision current protection.

Frequency standards play a vital role in modern science and technology and industry, in view of the problem of poor long-term stability of the constant temperature crystal oscillator affected by crystal aging and temperature and other factors, a constant temperature crystal oscillator frequency locking system based on phase-locked loop structure is designed, with the GPS signal received by the u-blox NEO-M8N module as the reference source, and the single-chip microcomputer STM32F103C8T6 as the control chip, and the frequency of the constant temperature crystal oscillator OC5SC25 is locked through the phase-locked loop structure. Using the extended Kalman filter and PID control algorithm, the long-term stability of the primary frequency standard and the short-term frequency accuracy of the secondary frequency standard are combined, and the test results show that the system realizes the frequency lock of the 10MHz constant temperature crystal oscillator, which can lock the frequency of the constant temperature crystal oscillator to a higher stability and accuracy. Its average frequency accuracy reaches 3.28×10^(-12), which is nearly 4 orders of magnitude higher than the initial frequency accuracy, which effectively improves the limitations of the constant temperature crystal oscillator in long-term stability.

For application scenarios that require multi-channel high-speed acquisition and stable synchronization between channels, a multi-channel synchronous acquisition scheme based on Field-Programmable Gate Array (FPGA) is designed and implemented. This scheme uses FPGA as the control and processing core,employs high-speed Analog-to-Digital Converters (ADC) to build sampling channels,and designs a stable clock and synchronization scheme,thus realizing a multi-channel synchronous acquisition system under high sampling rates. The feature of this solution is that it can monitor and adjust the synchronization status among multiple channels in real time, and it can be conveniently extended to synchronous acquisition among boards. Through testing, it is found that each time the system is powered on and off, the collected data among various channels is in a stable synchronous state.

High Definition Multimedia Interface (HDMI) technology is widely used in daily life.Therefore, the functional verification of the HDMI-CEC (Consumer Electronics Control) interface has become increasingly important. This paper designs and implements a verification platform for the HDMI-CEC interface based on the Universal Verification Methodology (UVM). The platform is capable of generating constrained random test excitations through its modular design, and the functional coverage and code cov-erage are used to evaluate the completeness of verification. The automated testing process and the coverage driven verification strategy of UVM are used in this paper, compared to traditional verification methods, significantly improving verification effi-ciency and accuracy. The core components of the verification platform are extended through UVM's standardized class library, ensuring the platform's reusability, scalability, and maintainability. The verification results show that the verification platform can effectively cover the various function points of the HDMI-CEC interface, so that the function coverage and code coverage are 100%, verify the validity and stability of the design. The research results of this paper provide an efficient and reliable solution for the verification of HDMI-CEC interface, offering significant engineering application value.

This paper proposes a spatial array-based processor core design where computing units communicate data via an interconnect bus and perform computations directly through local memory, eliminating the need for centralized register files. The processing results from local computing units are propagated to other units via a broadcast bus. This organization exhibits linear scalability, as the scale of computing units is not constrained by centralized components. It further incorporates flexible broadcast and reduction mechanisms that better align with algorithmic data communication patterns, facilitating efficient algorithm mapping and physical implementation. The processing element array implemented based on this design has high performance scalability, with a unit area performance of up to 1.4TOPS/mm2@INT8. It is suitable for large-scale deployment as a high computing power processor processing core.

High-speed SerDes rates have progressed from 56Gbps to 112Gbps and beyond. Preserving signal integrity at these ultra-high speeds while balancing power consumption, reliability, flexibility, and cost-effectiveness is a hot topic in current research. The latest research progress in key technologies related to 112G SerDes is deeply explored from four aspects—transmitter, receiver, clock structure, and low-power techniques—based on the current mainstream architecture of analog-to-digital conversion and digital signal processing. This exploration is provided as a reference for research related to high-speed SerDes technology.