At present, a single positioning technology cannot achieve good positioning results both indoors and outdoors. For example, Beidou positioning technology can achieve high accuracy in outdoor positioning, but its performance in indoor positioning is poor. Bluetooth has high positioning accuracy in indoor positioning, but it falls short in outdoor positioning. Based on the above situation, this article proposes an indoor and outdoor collaborative positioning technology based on Beidou and Bluetooth positioning. The Beidou and Bluetooth positioning systems are unified in the same coordinate system, and an improved BP neural network is used to achieve seamless switching in all scenarios. At the same time, a positioning fusion strategy is introduced for indoor and outdoor buffer areas to improve positioning accuracy. The experimental results show that in all scenarios, the average positioning error of the collaborative positioning system has increased by 0.7%, 31.7%, and 2.4% compared to a single positioning system, respectively, proving the effectiveness and accuracy of the method.

Unlike artificial neural networks (ANNs), spiking neural networks (SNNs), representing the third generation of neural network technology, perform computations based on the mechanisms of biological neurons. They use sequences of spike signals to transmit information, demonstrating significant advantages in energy consumption and high-speed processing of large-scale data. Currently, converting high-precision ANNs to SNNs is considered one of the most promising methods for generating SNNs. However, mainstream ANN-to-SNN conversion methods have their limitations: firstly, they do not support negative spikes, making it difficult to express negative spikes collected by dynamic vision sensor (DVS) cameras; secondly, it is challenging to achieve both low latency and high precision during the conversion process. To address these issues, this paper proposes a novel spiking neuron capable of globally representing both positive and negative spikes. Additionally, a stepwise Leaky ReLU activation function and a regional convergence testing algorithm are proposed to achieve zero-error conversion from ANN to SNN. With these methods, we achieve globally expressive, high-precision, low-latency, and highly robust ANN-to-SNN conversion. Our approach demonstrates outstanding performance on the CIFAR10 and CIFAR100 datasets.

In order to solve the problem that the output voltage of the charge pump is not adjustable, a charge pump circuit with controllable output voltage is designed, which is composed of a high-frequency oscillation circuit, a negative voltage generating circuit, a reference circuit and a feedback module. Compared with the traditional charge pump, the output voltage is more flexible, the output voltage ripple is smaller, and the overall circuit is based on the eastern 0.18 μm CMOS process. The simulation results show that the output voltage ripple is within 3mV at room temperature at an input current of 100μA. In the range of -40°C~125°C, the process angle output ripple is within 5mV. The charge pump circuit works stably at the output voltage of -3V~0V, and has been applied to the rail-to-rail op amp project.

T型栅PMOS器件因其强抗辐照能力，低寄生电容，逐渐成为RFSOI电路中必不可少的器件。而跨导是MOS器件中的一个关键参数，但T型栅PMOS器件的跨导会在栅极电压增大时，出现双峰效应，影响电路研制的判断。本文首先结合实测数据和3D TCAD仿真结果，深入剖析了T型栅PMOS器件跨导双峰效应的内部机理。并从温度、主栅尺寸和次栅尺寸三个方面分析阐述了其对双峰效应的影响。最终，基于T型栅PMOS器件版图结构，提出了一种可抑制双峰效应的改进结果，通过了仿真和流片验证，可以良好地适用于SOI工艺T型栅PMOS结构电路设计当中。

Before the mass production of chip engineering, it is necessary to conduct a comprehensive circuit performance test on the chip, screen the chips that meet the requirements, and avoid unqualified chips from entering the market. PMIC (Power Management IC) is a power management chip that realizes a variety of functions such as power conversion, power conversion, and current control through built-in DC-DC converters, current control, and protection mechanisms. Therefore, it is necessary to consider whether the technical indicators of the chip meet the requirements of use. In this paper, taking the UC3842 chip as an example, an analog chip performance test scheme based on Huafon STS8200 is proposed. In this paper, the test methods and test procedures of several important parameters of the chip (reference voltage, load regulation, linear regulation, oscillator frequency, rising and falling edge time, etc.) are studied. Finally, the experimental results of each parameter are within the range of effective values, and the results show that after testing 10 chips and LOOP100 the 10th chip, the test yield of the chip is 100%. It shows that the test scheme is real and effective.

To improve the SNR of frequency-hopping signal, a novel algorithm based on intrinsic time-scale decomposition is proposed. Firstly, the sampling signal is decomposed by ITD method to get rotational components and trend component. Then, the principle for noise judging is built by combing the ITD and the abrupt change of the cross-correlation peak between the rotational component and the original signal. Next, judging and deleting the noise components according to the principle. Finally, the signal is reconstructed with the rest of rotational components. Simulation results show that the algorithm is effective. To ensure that the distortion of the reconstructed signal is less than 5%, the algorithm can be adapted to -1 dB. The SNR of reconstructed signal is improved above 9 dB at least when the SNR of original signal is greater than -1 dB.

The selection of space components is crucial in the space mission. Due to the complexity and severity of space environment, the reliability and performance of space components are extremely high. Traditional component selection methods usually rely on expert experience and a single index evaluation, so it is difficult to fully consider the complex correlation and multi-dimensional performance specifications between components. The development of complex network theory provides a new idea for the selection of components, especially the community detection algorithm, which can help identify the potential relationship and group characteristics between components, so as to optimize the selection process and realize the accurate, fast, efficient and flexible selection of space components. In this paper, we will introduce the selection recommendation method of component selection based on complex network community detection algorithm, and propose the evolutionary algorithm based on module degree optimization. The algorithm introduces a maximum spanning tree coding method based on node similarity, a new method for generating initial populations and a sine-based adaptive variation function, and uses it in two component selection networks. The algorithm effectively detects the community structure in the selection network of components, and realizes the intelligent selection of components.

In this work, a temperature sensor designed for UHF implantable RFID chips was implemented using a 0.18μm process. The sensor employs MOS transistors as the temperature-sensing elements, with the core design based on a low-power temperature sensing circuit using subthreshold MOS transistors. The sensor utilizes Proportional To Absolute Temperature (PTAT) and Complementary To Absolute Temperature (CTAT) voltage delay generators to form a pulse width generation circuit, which produces pulse width signals that are quantified by a Time-to-Digital Converter (TDC). The core circuit layout area is 298×261µm², with a temperature measurement range of 35-45°C.Tape-out testing results indicated that, after two-point calibration, the maximum temperature measurement error across three chips was ±0.4°C, with a maximum error of ±0.2°C in critical temperature ranges. The measured power consumption was 623nW. Based on the tape-out results, the current chip's limitations were identified, and directions for future chip structure iterations were proposed.

This paper presents a detailed study of the hardware design and implementation of a Long-Term Post Filter (LTPF) based on the LC3 encoding protocol. The research includes an exploration of the fundamental principles of LTPF, the architecture of the hardware design, and its implementation and testing on an FPGA. The design was validated using an Altera MAX 10 development board, with results demonstrating significant improvements in processing efficiency and successful hardware acceleration of the LTPF with minimal resource consumption. Additionally, a comparison was made between the hardware implementation and a C-language fixed-point program on the STM32 platform, highlighting the advantages of the hardware design in terms of processing speed and resource utilization. The findings suggest that, while the current design outperforms the software architecture, there remains potential for further system performance enhancement through optimization of the logical design.

In order to improve the measurement accuracy and resolution of the phase-sensitive receiver, an all-electronic phase-sensitive receiver based on the all-phase Fast Fourier Transform (apFFT) algorithm was designed. The hardware is a two-take-two Dual-Channel structure, and the process is synchronized by two machines, and the calculation results are output after comparison. The DDS generator was used to build a test platform, the function of the scheme was simulated and verified, and the on-site track circuit combination frame was connected to the field test. The experimental results show that the design can accurately detect the occupancy state of the train in the track section, distinguish the random noise and harmonic signal on the rail. It’s anti-interference ability is excellent, and the phase difference measurement error is less than 0.3°. This scheme is an electronic improvement of the existing microelectronic phase-sensitive track circuit receiver, the circuit is simple, the phase difference calculation is completely completed by software, the reliability is high, and it can be used for the coded or non-coded section of the 25Hz phase-sensitive track circuit using 50Hz alternating current traction.

Real-time is a crucial feature in embedded test platform development, as it enables the platform system to respond quickly to task events. In most cases, there are many tasks running on the platform and different types, so in order to solve the problem of how to prioritize the execution of real-time tasks when there are many tasks and the relationship between tasks is diverse, this paper proposes a multi-DAG real-time priority scheduling algorithm (MDRTPS), which is mainly divided into three steps: (1) real-time task separation for multiple DAGs, The separated real-time task set and the normal task set use different priority algorithms and resource allocation. (2) Maintain three scheduling queues, and the queues coordinate the ordering between different DAG tasks, and (3) the last scheduler schedules tasks to the processor core based on the earliest completion time. Experimental results show that the MDRTPS algorithm is better than the HEFT algorithm and CPOP algorithm in terms of task span and response speed of real-time tasks.

The analog source holds an important position in the test and calibration system of radio radar equipment. The beacon machine equipped with a certain type of Doppler radar has defects such as being bulky and heavy, and being unable to simulate Doppler signals, making it difficult to meet complex test requirements. Therefore, a small dynamic analog source based on the implementation of FPGA was designed. This analog source, through the collaborative operation of FPGA and digital DAC, achieves rapid frequency adjustment, enabling the carrier signal to superimpose Doppler information. In addition, the signal frequency and amplitude generated by the analog source have flexible control methods. It can not only be adjusted wirelessly and in real-time but also output according to pre-stored data, effectively compensating for the deficiencies of the original beacon machine and providing strong support for the test and calibration work of radar equipment.

The travel and daily activities of visually impaired individuals typically rely on walking sticks, guide dogs, or assistance from others. However, with the advancement of urban planning due to economic development, the complexity of urban layout and road design has significantly increased. Consequently, these traditional methods are no longer sufficient to meet the daily needs of blind individuals. Therefore, it is crucial to prioritize attention towards the visually impaired community and enhance their quality of life. This design focuses on machine vision techniques for denoising, filtering, and target calibration in color information and depth images. Subsequently, machine learning training is employed to achieve image-based functions such as color recognition, obstacle detection, and distance measurement. The analysis results are then converted into audio signals which are outputted through voice feedback to provide users with walking suggestions while alerting them about obstacles that cannot be observed in advance. The ultimate goal is to offer obstacle avoidance services for visually impaired individuals by minimizing the impact of unforeseen obstacles during mobility.

To address the issues of high resource utilization and poor customizability associated with using pre-built AXI interface IP cores, a phased, self-designed approach is proposed to add AXI bus support to a designed MIPS processor core. The design is implemented using Verilog HDL for writing RTL code. The overall logic functionality of the processor was verified in the Vivado simulation environment, and the bitstream file was downloaded to the FPGA development board for prototype verification. Resource utilization and timing were obtained. Finally, the processor was synthesized using the Design Compiler (DC) tool, and the overall area and power consumption of the processor were evaluated. The verification results indicate that the self-designed AXI bus consumes less resources and area compared to directly using an AXI interface IP core. This approach ensures that the AXI bus is added without changing the processor core architecture, significantly reducing the difficulty of replacing the original interface in the processor core with the AXI bus interface. It not only reduces integration complexity but also ensures a high degree of customization to meet specific system requirements and performance demands.

电子档案数据量通常较大，结构也比较复杂，跨域检索时需要设计高效的数据存储和检索方案，以提高检索准确度。为此，提出了基于云存储的电子档案数据跨域安全检索算法研究。在最优存储节点下，利用云存储节点分别向不同区域的存储节点传输一个电子档案文件，利用分层原理，计算跨域节点之间的距离，通过阈值分级确定云存储节点的数量，分层存储电子档案数据。采用Fourier变换方法，查询重复电子档案数据，在Fourier变换域，重建电子档案数据，给出需要删除的数据，结合逆变换处理，计算出数据的4阶混合累积，完成电子档案重复数据的删除。将聚类中心与所有电子档案数据之间的平均关联度作为电子档案数据的检索空间，确定满意度向量，判断检索空间中电子档案数据的满意度，采用梯度法修正满意度向量，根据用户检索关键词的关联度，实现电子档案数据的跨域安全检索。实验结果表明，文中算法对电子档案数据的自相关检索性能较好，可以将跨域安全检索的查准率提高到90%以上。

Sensors often employ metals or semiconductors as their sensitive components.When semiconductor materials are subjected to external optical or thermal stimuli,their electrical conductivity undergoes significant changes,leading to temperature drift in the sensor’s output signals.This temperature drift severely impacts the measurement accuracy and application scope of sensors.To enhance their temperature ability,temperature compensation is essential.Pressure sensors,due to factors such as the piezoresistive coefficient being influenced by temperature,and the temperature sensitivity coefficient is typically negative.The design employs a constant current source with a positive temperature coefficient as the excitation driver for the sensor.The Wheatstone bridge,after being compensated through series and parallel resistance methods,is then utilized to perform sensitivity temperature compensation on the sensor.Experimental results have demonstrated that after undergoing compensation from this two-stage circuit,piezoresistive pressure sensors exhibit stabilized output signals within a range of -50℃ to 75℃,with errors reduced to less than 0.35%FS .This approach effectively mitigates the impact of temperature drift,thereby enhancing the sensor’s overall performance and reliability across a broader temperature spectrum.

For the conventional radar target clutter detection technology, the background power level estimation of each azimuth-distance unit is obtained by the recursive update of the continuous scanning period samples in the resolving unit, but this estimation method fails when there are a large number of interfering target samples in the continuous scanning period samples of the resolving unit. In this paper, this paper draws on the sample screening technology in the spatial constant false alarm to the time domain constant false alarm, and proposes an OTSU-CCA-based clutter detector to improve the accuracy of background power level estimation by eliminating the possible interference target samples in the continuous scanning period samples, and then improve the detection performance of clutter map.