针对在真空强电磁干扰环境下，微弱推力测量信号易被噪声淹没而导致测量精度低、动态响应差的问题，本文提出一种基于卡尔曼滤波与电磁屏蔽相结合的信号降噪优化方案。该方案通过构建多层复合电磁屏蔽系统，从物理层面抑制空间辐射干扰；同时，建立测力计系统的动力学模型，并应用卡尔曼滤波算法对采集信号进行最优状态估计，以分离确定性推力信号与随机过程噪声和测量噪声。实验结果表明，该方案能够将信噪比（SNR）提升近30dB，与传统低通滤波相比，在有效抑制噪声的同时，显著改善了系统的动态响应特性，为高精度、高动态范围的微推力测量提供了可靠的技术途径。

This paper presents the design of a high-speed real-time signal processing radar digital front-end based on Xilinx FPGA.The FPGA in this radar front-end fully utilizes its abundant resources, including logic, RAM,DSP, and high-speed interfaces, to implement functional modules such as 10-Gigabit Ethernet, Microblaze, and high-speed cache. This enables the FPGA to perform control, preprocessing, and high-speed data transmission, resulting in a radar processing front-end with a simple hardware structure, high signal processing capability, and fast data transmission speed. In software implementation, the high-speed data read-write timing is meticulously designed according to radar waveform characteristics to meet the data transmission capacity requirements. It has been successfully applied in real-time processing for surveillance radar projects, achieving excellent results

A two-stage operational amplifier with low input bias current, rail-to-rail input, high gain, and high bandwidth has been designed by combining a folded-cascode first stage with a class-AB output stage, incorporating a linear transconductance (Gm) loop and gain-boosting techniques. The first stage employs a folded-cascode architecture, achieving rail-to-rail input through parallel NMOS and PMOS input differential pairs. A dedicated current compensation scheme ensures a constant output impedance of the first stage. The second stage utilizes a class-AB output configuration, where a translinear loop precisely sets the quiescent current of the output stage, resulting in improved drive capability and reduced power consumption. Gain-boosting techniques are applied to further enhance the output impedance of the cascode structure, thereby increasing the overall DC gain. The op-amp is fabricated in a SMIC 180nm MS BCD CMOS process.After tape-out, a test platform was independently developed by designing the test circuitry and fabricating a custom PCB board. Key parameters of a broadband low-input-bias-current operational amplifier, including input bias current, offset voltage, open-loop gain, small-signal bandwidth, slew rate, and noise, were measured using an oscilloscope, network analyzer, and spectrum analyzer. Test results demonstrate that with a 2pF load capacitor, the amplifier achieves a low-frequency gain of 50dB and a gain-bandwidth product (GBW) of 380MHz.

The selection of aerospace components is a critical link in space missions. Traditional selection methods are plagued by issues such as low efficiency and high reliance on professional expertise. This paper designs and implements an intelligent selection and recommendation system for aerospace components based on large language models (LLMs) and retrieval-augmented generation (RAG) technology. Adopting an agent-based architecture, the system achieves end-to-end intelligent processing, converting users' natural language requirements into component recommendation schemes seamlessly. A professional knowledge base is constructed, encompassing 468 aerospace-grade components and 60 system-level bills of materials (BOMs). A multi-strategy cascaded retrieval mechanism integrating exact matching and semantic understanding is designed, and an hallucination prevention and control mechanism is developed to meet aerospace safety requirements. The system is capable of handling application scenarios including single component recommendation and system-level scheme generation. In an evaluation experiment involving 65 test cases, the system achieves a macro-average F1-score of 0.829, representing a 10.4% improvement over manual keyword retrieval and a 69.5% improvement compared to pure LLM methods, thus verifying the system's effectiveness. The intelligent selection and recommendation system for aerospace components proposed in this paper can effectively support the intelligent selection of aerospace components.

This paper presents the design and implementation of a highly efficient and stable electromagnetic wave energy harvesting circuit targeting ultra-high-frequency (UHF) RFID applications. The system consists of a rectifier, a reference circuit, and a voltage regulator, collectively providing a reliable power supply for other chip modules. Key achievements include: a differential rectifier achieving 67% power conversion efficiency (PCE) with 1.84 V output at -11 dBm input power; an ultra-low-power CMOS reference circuit with temperature coefficients of 34.9 ppm/°C (voltage) and 18.4 ppm/°C (current), and a power supply rejection ratio (PSRR) better than -93 dB at 100 Hz; and an LDO-based voltage regulator exhibiting a load regulation of 41.28 mV/mA under varying load conditions. Additionally, clock, reset, demodulation, and modulation circuits are integrated. The circuit is implemented in a 180 nm CMOS process, occupying a layout area of 341μm × 346μm. Post-layout simulations indicate a total power consumption of 6 μW. Silicon measurements confirm that all performance metrics meet the requirements for high conversion efficiency and power supply stability in UHF RFID chips.

Facing the processing performance bottleneck of current satellite communication terminals in high-throughput IP service scenarios, this paper proposes a high-speed IP service transmission method based on a CPU+FPGA SoC architecture. The core of this method lies in the separation and cooperation of the control plane and the data plane: functions required for high-speed data forwarding, such as IP access, route addressing, and link frame assembly/disassembly, are offloaded to the FPGA to form a high-performance data plane; control plane logic such as route maintenance and protocol interaction is handled by the CPU. Through key technologies like event-driven synchronization and hardware-level QoS scheduling, engineering challenges in collaborative design, such as entry synchronization and low-latency signaling guarantee, are overcome. This achieves a significant performance leap on existing hardware, providing an effective solution for the smooth performance upgrade of large-scale in-network satellite terminals and the design of compact, low-power terminals.

For the hot backup working mode of dual-channel redundant electronic controllers, a design scheme of a multi-functional channel management module based on CPLD is proposed to achieve efficient data exchange and synchronization between primary and backup channels. Serial Peripheral Interface (SPI) is used for communication and synchronization, with the management module serving as the SPI communication host to implement data broadcasting to both primary and backup channels and direct bridging between them, while also possessing the capability to monitor communication data. Based on simulation verification, the serial communication management functions normally, with the delay caused by timing logic in SPI bridging and broadcasting being 30ns, indicating good system real-time performance. Tests on the SPI data transmission function of the designed dual-channel redundant electronic controller show that data integrity is good in both serial loopback and SPI data exchange tests, meeting the design requirements.

Stochastic computing (SC), an unconventional computational paradigm, employs probabilities to represent numerical values. This representation enables complex arithmetic operations to be performed using simple logic gates. This work presents a fast unary median filtering circuit design. The proposed filter utilizes counters to generate stochastic numbers (SNs) and constructs fundamental sorting network units using stochastic correlation logic. A feedback loop, formed based on the output, dynamically terminates computations early without consuming additional hardware area, significantly reducing substantial circuit latency. Experimental results demonstrate that the proposed median filter design outperforms existing implementations in both actual bitstream length and energy consumption. Specifically, the proposed 3×3 window median filter circuit achieves a 55.58% reduction in energy. Further validation using median filtering on images corrupted by salt-and-pepper noise confirms the accuracy of the proposed circuit. For a 16-input sorting network application, the proposed design exhibits lower consumption when inputs range within [0, 0.5], achieving up to a 50% reduction in actual bitstream length and energy consumption.

With the wide application of Field Programmable Gate Arrays (FPGAs) in high-performance computing, artificial intelligence inference, and 5G communications, the scale of circuit designs and the complexity of timing constraints continue to increase, placing higher demands on the runtime efficiency of Static Timing Analysis (STA). Existing FPGA STA tools predominantly rely on single-core or multi-core Central Processing Unit (CPU) architectures. Although continuous algorithmic optimizations have been made, they still face computational bottlenecks and insufficient memory access efficiency when handling large-scale FPGA designs. In recent years, Graphics Processing Units (GPUs), with their massive parallel computing capabilities, have provided new opportunities for improving FPGA STA performance. However, challenges in memory access patterns under heterogeneous GPU architectures, optimization for timing graph loop detection, and heterogeneous parallel acceleration strategies limit the effectiveness of current GPU-accelerated methods in FPGA STA scenarios. To address these issues, we propose an FPGA STA algorithm accelerated by an efficient heterogeneous parallel strategy. First, targeting the problem of discontinuous memory access and field interleaving in traditional object-oriented data structures under CPU-GPU heterogeneous architectures, a structure-of-arrays (SoA)-based data layout strategy is presented. Combined with data reordering operations, this approach effectively reduces memory access latency and improves bandwidth utilization, providing a data foundation for high-performance FPGA STA computational engines. Second, to overcome the limitations of low efficiency and poor robustness in timing graph loop detection, a parallel loop detection optimization algorithm based on color propagation is designed, enabling efficient acceleration in the preprocessing stage of FPGA STA. Furthermore, a task decomposition and timing graph traversal method tailored for CPU-GPU heterogeneous architectures is proposed, achieving efficient acceleration of core STA operations such as delay calculation, levelization, and graph propagation. Finally, experimental results on both the OpenCores and industrial-grade FPGA benchmarks demonstrate that, compared with traditional CPU implementations, the proposed method achieves a runtime speedup of 3.125× to 33.333×, with overall performance surpassing that of the OpenTimer tool. This research provides a practical and feasible approach for efficient timing verification in large-scale FPGA designs.

In response to the issues such as the reduction in the acoustic wave intensity emitted by the ultrasonic transducer and the decrease in the sensitivity of the received signal of traditional ultrasonic anemometers under conditions like rain and snow, strong wind, dusty environments, and long-term usage, which subsequently lead to low measurement accuracy and low stability of wind speed and direction, an ultrasonic anemometers based on adaptive adjustment of signal gain has been designed. The electrical hardware section mainly consists of the driving circuit and receiving circuit for ultrasonic signal transmission, the programmable signal gain amplification and adjustment circuit, the filtering circuit, the AD acquisition circuit, and the MCU control circuit, etc. The software part mainly employs the time difference method, the ring tone method, the cross-correlation method, and the adaptive adjustment control algorithm of signal gain based on the binary search method to calculate the wind speed and direction. Experimental results indicate that the designed ultrasonic anemometer yields highly accurate and stable data for wind speed and direction measurements in harsh environments，Within the range of 0-15m/s, the error is ±0.5m/s; for wind speeds between 15-40m/s, the error does not exceed ±3%.The absolute error of wind direction is less than 3°.

CPLD器件的严格使用场景对其提出了高可靠性测试要求，针对上位机测试CPLD器件过程繁琐、测试效率低等问题，提出了一种基于逻辑分析仪的CPLD配置向量生成方法。该方法以国产CPLD为例，利用逻辑分析仪实时采集JTAG下载配置数据，通过协议解码和对解码后的配置数据深入分析和总结，基于SVF标准语句格式编写生成了配置向量，完成了配置向量转码和ATE在线配置测试验证，测试结果有效证明了生成配置向量的正确性和该生成方法的可行性，对后续CPLD器件使用ATE自动化量产测试具有重要指导意义。

This paper presents a low-noise, high-voltage, high-output-current power operational amplifier designed in a SMIC 180 nm BCD process. The architecture features a low-noise PMOS input stage, a voltage gain stage, and a Class AB output stage biased by a transconductance linear loop. Stability is ensured by Cascode frequency compensation, while integrated hysteretic over-temperature and current-limiting circuits provide robust protection against thermal and electrical damage. Combining 60V DMOS and 1.8V CMOS devices, the amplifier operates over a wide supply range of ±4V to ±30V and a temperature range of -55°C to +125°C. Simulation results demonstrate an equivalent input voltage noise of 8.85 nV/√Hz, a 400mA output current, 143.3dB DC gain, a 6.804 MHz unity-gain bandwidth, a 33.7 V/μs slew rate, with the chip area of 1.79 × 1.12 mm². The proposed amplifier is well-suited for vehicle electronic applications including precision battery sensing, sensor interfaces, and power device driving.

To address the challenges of traditional MOSFET testing, such as cumbersome procedures, reliance on bulky instruments, and a low degree of intelligence, this paper presents an automated test system integrating a Large Language Model (LLM) with the "Yuzhu S" portable hardware. Centered around the "Yuzhu S" instrument, the system performs characteristic curve, switching time, and double-pulse tests using an integrated PCB carrier board. It innovatively leverages the Gemini API to empower the software, enabling automatic parsing of PDF datasheets, intelligent recommendation of test parameters, and in-depth error analysis of the results. The test results for an IRF7401 device demonstrate that the key static and dynamic parameters obtained by the system show excellent agreement with datasheet specifications and simulation values, thus validating the accuracy and feasibility of the proposed solution. This research provides an efficient, intelligent, and portable new method for end-users to evaluate device performance.

Aiming at the constraints of time and venue in FPGA-related experimental teaching, as well as the difficulty of collecting process data on teaching and learning in traditional offline on-site board-level experiments, this paper presents the design and implementation of a remote laboratory system for digital-circuit instruction based on the Unisoc FPGA platform. By adopting a hardware–software co-design philosophy, the system not only supports remote download/update via a emulated JTAG interface, bit-stream flashing, waveform capture and signal generation, but also extends to a dual-channel arbitrary waveform generator and spectrum analyzer. Integrating remote cameras and digital-twin technology panels, the system streams real-time experimental phenomena over Ethernet, enables remote interaction and continuous monitoring of experiment status, and thus establishes an immersive and scalable remote laboratory environment.

To tackle the concurrent challenges of bandwidth, linearity, and integration in the analog front-end (AFE) of a 100-Gbps PAM-4 wireline receiver for Chiplet interconnect applications, this paper presents a high-performance AFE architecture based on a transconductance–transimpedance amplifier (GM-TIA) continuous-time linear equalizer (CTLE). The proposed AFE efficiently compensates for channel loss while maintaining high linearity through an integrated broadband input matching network consisting of an asymmetric T-coil, a programmable attenuator, and an AC coupler. A two-stage cascaded GM-TIA-based CTLE enables wide-range gain tuning from low to high frequencies and also serves as a variable-gain amplifier (VGA). Designed in a 28-nm CMOS process, the AFE occupies a core area of 0.012 mm² with the power dissipation of 9.94 mW. The equalization tuning range extends from 2.25 dB to 13.39 dB. After equalization, the 100-Gbps PAM-4 output exhibits an eye height greater than 100 mV and an eye width exceeding 0.52 UI.

Front-end RTL design is a critical phase determining a chip's performance, power, and area (PPA). Conventional methodologies often prioritize functional implementation, lacking systematic optimization for PPA metrics. To address this, this paper proposes a multi-dimensional RTL optimization approach—the DCAP co-optimization model. This model establishes a framework encompassing four dimensions: Data-path (D), Computation (C), Area-management (A), and Power-management (P). Using the USB 2.0 link layer as a case study, data throughput is enhanced via a coupled handshake scheme, computational efficiency is optimized using a real-time iterative CRC architecture, area overhead is controlled through resource management, and power consumption is reduced by improving clock gating coverage. Back-end implementation results based on TSMC 65nm technology demonstrate that the design achieves a throughput of 52.3 MB/s (protocol efficiency:87%) in High-Speed mode, with a power consumption of 0.156 mW and an area of 3333.6 μm². Compared to the pre-optimized design, this represents a 39% reduction in power and a 23% reduction in area. In conclusion, the proposed DCAP model provides a reusable methodological guide for addressing PPA optimization challenges in digital circuit design at the register-transfer level.

Large Language Models (LLMs) face dual challenges in automated hardware design: ensuring functional correctness and achieving human-expert-level optimization efficiency. Circuits generated by existing models often suffer from a fundamental "Boolean optimization barrier," resulting in a gate count that is 38% to 1075% higher than human-expert designs. To address this, we introduce VeriOptima, a novel two-stage AI framework designed to bridge the gap from natural language specifications to highly-optimized gate-level netlists. The first stage, ReasoningV, is a high-fidelity Verilog generation model that ensures functional correctness through a high-quality dataset and an adaptive reasoning mechanism. Its performance was independently evaluated, achieving a 57.8% pass@1 accuracy on the VerilogEval-Human benchmark, which is competitive with top-tier state-of-the-art (SOTA) models. The second stage, CircuitMind, is a multi-agent optimization framework that takes the code generated by ReasoningV and refines it to human-competitive efficiency. For rigorous evaluation, we introduce TC-Bench, the first gate-level benchmark derived from a competitive circuit design platform. Experiments validate the effectiveness of our integrated framework. ReasoningV achieves state-of-the-art performance among open-source Verilog generation models. More critically, in comparative compilation-optimization experiments, using designs from ReasoningV as a starting point yields significantly better final Power, Performance, and Area (PPA) metrics than when starting with code from other LLMs. Ultimately, after refinement by CircuitMind, 55.6% of the implementations reach or surpass the efficiency of top human experts. This work presents the first end-to-end solution to systematically overcome the challenges of both generation and optimization, paving the way for fully automated, high-quality circuit implementation. The related code has been released on GitHub:ReasoningV（https://github.com/BUAA-CLab/ReasoningV）and CircuitMind（https://github.com/BUAA-CLab/CircuitMind）。

Field-Programmable Gate Arrays (FPGAs) are key platforms for edge computing and have broad potential in edge-side image recognition. This paper presents an embedded system based on a domestically produced FPGA and a self-designed ASIC-like architecture for real-time edge deployment. On the software side, a lightweight neural network named NexusEdgeNet is proposed. It achieves 94.22% accuracy on 39 farmland disease categories with only 0.184 MB of parameters. On the hardware side, an ASIC-like accelerator fully described in Verilog is designed. It adopts a distributed on-chip memory structure, eliminating external memory access, and supports arbitrary-shaped convolution, pooling, and fully connected operations. Several optimization techniques are applied, including near-memory parallel computing, pipelining, sliding convolution windows, and double buffering. The accelerator reaches 399 FPS inference speed on the EP6HL130 FPGA, with 85% resource utilization and significantly reduced logic consumption. The system integrates image acquisition, processing, and display, supporting real-time video stream recognition. It maintains high accuracy while achieving excellent real-time performance and resource efficiency. This work provides a practical, low-cost solution for edge computing applications based on domestic FPGAs.

To address the high-precision requirements for resolver excitation current peak control, this paper designs and implements a high-precision excitation current peak control system based on distributed Delay-Locked Loop (DLL) timing control. By integrating a 7-stage low-offset, high-bandwidth Programmable Gain Amplifier (PGA), a 13-bit hybrid-timing-logic-based Successive Approximation Register Analog-to-Digital Converter (SAR ADC), a 12-bit digital Sinusoidal Pulse Width Modulation (SPWM) module employing a bipolar modulation architecture, and three sets of DLL timing control circuits on-chip, a complete closed-loop excitation current control system is constructed. This system achieves precise sampling and dynamic adjustment of the excitation current peak. Experimental results demonstrate that the designed PWM waveform output achieves a resolution of 1.3 ns and an excitation current peak error of less than ±0.934% at a target current of 400 mA, providing an effective solution for resolver excitation current peak control.

针对绝缘栅双极型晶体管（IGBT）功率模块在高速开关过程中产生的近场磁辐射干扰问题，本文采用仿真与实验相结合的方法，对模块内部的空间磁场分布规律进行了系统性研究。首先，基于磁矢量势（MVP）理论，利用自主开发的有限元求解器对GCV900系列IGBT模块进行三维电磁场建模与仿真，分析了不同频率下模块内部的磁场分布特性。随后，搭建了三相无功测试平台，通过高精度近场磁探头对模块上不同位置的IGBT芯片表面的磁场进行了实验测量。仿真与实验结果均表明：近场磁辐射强度在模块内部呈不均匀分布，靠近直流输入端、处于主换流路径核心位置的IGBT芯片区域承受的磁场辐射最强，而靠近交流输出端的芯片区域所受影响最小。 本研究揭示了IGBT模块内部磁场辐射的分布规律，为功率模块的电磁兼容优化设计及近场耦合干扰抑制提供了理论依据和数据支持