在国产自主化加速推进与AI算力需求爆发的双重背景下，存储底层盘控核心技术国产化依然不足。针对这一问题，本文设计并实现了一套基于国产软硬件生态的SATA标准NAS存储系统，其核心硬件架构采用复旦微FPGA与龙芯3A3500处理器，软件层面依托银河麒麟操作系统。其中，FPGA实现了PCIe与SATA协议的桥接转换，主要包括PCIe高速数据交互、HBA控制器逻辑与SATA协议处理等核心功能。在此基础上，进一步结合RAID冗余存储技术，设计并实现了集卷组管理与多协议文件共享于一体的NAS存储管理系统，为存储国产化提供了一种可行的技术路径和落地方案。

Facing the new era's cybersecurity situation, China has timely proposed an active immune protection system based on trusted computing 3.0. Combined with the national standard specifications of the Trusted Platform Control Module (TPCM) in China, a TPCM module solution based on a secure SSD and its implementation method are proposed. Through the built-in SM2, SM3, SM4, random number generator module, and OTP controller module of the security control chip, the power-on self-test, secure boot, data encryption and decryption, and key management functions of the security control chip are realized. Based on the secure SSD, an authentication software is designed to achieve the trusted boot measurement and response of the physical environment such as the computer motherboard, BIOS, peripherals, and IP address. Compared with the existing TPCM cards, the proposed solution has the advantages of high security, good compatibility, strong scalability, convenient deployment, and low cost.

星载合成孔径雷达(Synthetic Aperture Radar,SAR)实时成像处理需在星上资源严格受限、空间辐照恶劣条件下，实现多模式、大运算量计算。研制专用SAR 成像处理SoC（System on Chip）芯片，通过专用计算引擎电路实现算法加速，可有效提高实时成像处理效率。专用芯片设计过程中，需验证其功能边界及异常场景，而如何提升专用算法加速电路的验证覆盖率是核心难题。本文提出一种基于细粒度电路匹配建模的SAR成像处理芯片的验证方法，对每个计算引擎建立独立的细粒度参考模型，在实现运算功能基础上增加对电路运算精度、电路执行优先级等特征建模，解决了传统参考模型无法用于SAR计算引擎数据比对难题；在此基础上基于UVM（Universal Verification Methodology）构建可复用、可扩展的验证环境，采用算法功能加随机配置的双组合验证策略。经测试试验，本文方法可将计算引擎验证覆盖率提升14%~30%，满足SAR实时成像处理应用需求。

针对工业领域对高效率、低功耗的嵌入式三维测量系统的迫切需求，设计了一种基于半周期条纹二值编码算法架构的FPGA三维测量系统，首先通过相机控制模块采集结构光图像，并对图像进行缓存和滤波预处理。随后利用FPGA并行运算的优势实现了包裹相位、相位展开和三维重建等关键算法模块的硬件加速。最后通过千兆以太网模块将重建结果传输至上位机进行可视化显示，构建了完整的嵌入式三维测量流程。实验表明，所提系统在处理单组720*540分辨率的图像单次重建速度为4ms，系统功耗为1.687W，对标准小球测量的拟合误差为0.0532mm，可见该系统在保持低功耗的同时具有良好的鲁棒性与实用性，为嵌入式三维测量系统的实现提供了可行的解决方案。

To address the complex challenges of modern new energy vehicles, such as low network transmission latency and high real-time data requirements, a vehicle gateway controller based on CAN FD (Controller Area Network Flexible Data-rate) was designed using Renesas automotive-grade microcontroller RH850/F1K. It features six bus channels, supports both classical CAN and CAN FD, and includes data storage functionality. The bus transceiver employs the next-generation CAN transceiver TJA1462 to enhance signal transmission performance. The software design is based on the embedded operating system FreeRTOS, enabling multitasking and structured hierarchical functions. Additionally, a specialized driver was developed for the CAN peripheral's unique transceiver method on the RH850/F1K microcontroller. Using a USB-to-CAN tool, the gateway's data transmission and storage capabilities were tested. The results demonstrate that the designed gateway controller can operate stably even when the load rate approaches the bus usage limit, providing an efficient and reliable solution for vehicle gateway controllers.

Ensuring the structural integrity of bridge expansion joints is critical for maintaining traffic safety and prolonging infrastructure lifespan. However, conventional inspection methods are often labor-intensive, time-consuming, and disruptive to traffic flow. To overcome these limitations, this study proposes an edge–cloud collaborative acoustic monitoring system for the long-term health assessment of bridge expansion joints. Over an 18-month monitoring period spanning multiple bridges, approximately 21,000 acoustic signature samples of bridge expansion joints were collected. To ensure accuracy and reliability, all samples were meticulously annotated by experienced highway engineers. Based on this dataset, an adaptive edge–cloud collaborative classification framework was developed. Specifically, the edge device employs a cascade classification model based on Support Vector Machines (SVM) for real-time, lightweight inference, while the cloud leverages a deep learning model based on Gated Recurrent Units (GRU) to perform more complex analysis. The cascaded classification model deployed on the edge device achieved an accuracy of 96.7%, with a 95% confidence interval (CI) of (0.9632, 0.9668). In comparison, the GRU-based classifier running on the cloud attained a higher accuracy of 98.2%, with a 95% CI of (0.9783, 0.9823). Furthermore, the proposed adaptive two-stage classification strategy reduced data transmission to less than 5% of the total collected data. These experimental results demonstrate that the proposed system offers a reliable, efficient, and accurate solution for the acoustic health monitoring of bridge expansion joints.

The Host Port Interface (HPI) of an independently developed Digital Signal Processor (DSP) is the core channel for large-scale data interaction between the host and the DSP, allowing the host to directly access the DSP's memory space through a parallel bus, significantly enhancing the efficiency of data exchange. The limitations of the HPI interface in terms of bandwidth, portability, and compatibility with the Enhanced Direct Memory Access (EDMA) interconnection protocol are addressed in this paper, and a complete 16-bit HPI interface based on the Advanced High-performance Bus (AHB) protocol is proposed and designed. The design adopts a modular approach and is implemented in Verilog, including the register configuration module, AHB slave interface module, read cache and control module, host port interface module, and write cache and control module. Functional verification and logic synthesis of the host's read and write access to the HPI were conducted. The synthesis report indicates that at a 40nm process and 200MHz operating frequency, the overall area of the HPI interface based on the AHB bus is 10344µm², with a bandwidth of 66MB/s and a dynamic power consumption of only 0.386mW. The verification results show that the HPI interface, while achieving data transmission, realizes burst data transmission between the AHB protocol and EDMA, providing a high-bandwidth, easy-to-implement host parallel communication interface with stronger portability and universality.

Aiming at the problems such as the limited on-chip resources of the self-developed DSP (Digital Signal Processor) and the insufficient storage space for large-scale data and programs, a configurable External Memory Interface (EMIF) design scheme is proposed and designed. This scheme achieves flexible access to three types of memory, namely asynchronous memory, SDRAM and SBSRAM, through four configurable chip selection space registers, and realizes efficient data transmission between the CPU and external memory by using an enhanced direct memory access module. By writing a testbench and comparing the consistency of read data and written data, EMIF has undergone a relatively thorough functional verification. The experimental results show that this design realizes the read-write burst access of 8/16/32bit data. Under the 40nm low-power process, the area is 25,119.36μm2 and the power consumption is 1.296mW.

As electronic packaging technology advances towards high-density and highly integrated configurations, FC-CCGA packages are increasingly adopted in aerospace and other high-reliability applications due to their superior electrical and thermal performance and I/O density. These packages must withstand vibrational loads during launch and thermal cycling during in-orbit operation, with their core interconnect components susceptible to stress accumulation leading to thermomechanical fatigue failure, directly threatening the reliability and lifespan of the package devices. This study, based on the Anand model, constructs a comprehensive electro-mechanical 3D model encompassing chip bumps, solder columns, epoxy resin, and PCB substrate, systematically investigating the vibration and thermal fatigue reliability of FC-CCGA solder joints and bumps. The analysis includes impact response spectrum assessments pre- and post-electrical reinforcement, simulating the stress-strain response of critical solder joints and bumps under thermal cycling loads, and evaluating the plastic strain distribution and evolution over time. Additionally, the Coffin-Manson model is employed to predict thermomechanical fatigue life of the solder joints and bumps. Temperature cycling tests on packaged devices were conducted, observing morphological changes in solder joints at varying cycle counts; the experimental results align with simulation predictions, providing a theoretical basis and methodological support for optimizing solder joint structures and assessing their lifespan for high-reliability applications.

To achieve independent controllability and enhance the communication reliability of the EtherCAT Slave Controller (ESC), this paper proposes an FPGA-based redundant communication interface. The design adopts a modular architecture with innovative integration of hardware modules, including link redundancy processing, multi-path frame forwarding, EtherCAT frame parsing, and configurable timing compensation. It supports dual-link redundancy backup and enables real-time detection and isolation of erroneous frames. The system performs automatic frame forwarding and achieves microsecond-level latency through parallel hardware processing. FPGA test results demonstrate that the interface maintains stable communication during single-link failures while consuming minimal hardware resources. The proposed solution effectively improves the fault tolerance and real-time performance of ESC communications, laying a solid technical foundation for the independent development of high-reliability industrial communication chips.

Short-wave infrared (SWIR) imaging technology, operating in the 1 μm–2.5 μm electromagnetic spectrum, does not rely on object thermal radiation, is less affected by ambient illumination, fills the gap in full-band imaging, and holds significant value across multiple fields. This design develops an uncooled SWIR camera core system based on the ZYNQ platform and a domestic InGaAs focal plane array (FPA) detector to realize image acquisition, preprocessing, and transmission: hardware encompasses a main control board, driver board, TEC temperature control, power supply, and peripheral circuits, with output channels established via Camera Link and Ethernet, while software achieves PL-PS data interaction, completes link synchronization and data reception based on the JESD204B protocol, and optimizes image quality through an improved preprocessing algorithm. The system achieves stable output of 640×512 resolution at 30 fps, boasting light weight, low power consumption, and low cost, which fully meets practical application requirements.

FPGAs are extensively employed as interface boards in embedded systems. The software operating on these chips primarily interacts with peripheral devices. A significant challenge in verifying such FPGA software lies in developing configurable simulation models (supporting both normal and abnormal operations) based on peripheral chip specifications. Currently, these simulation models are predominantly implemented as static constructs using System Verilog/Verilog-HDL/VHDL language features. These simulation models, akin to RTL models, exhibit a structured nature. This implies that their configuration is static; they do not support dynamic instantiation or teardown during the course of simulation based on runtime needs. Therefore, this type of simulation model is suitable for verification scenarios in which the chip's operating mode remains unchanged during runtime. For verification scenarios where the operating mode needs to switch during runtime, using a static simulation model to simulate such scenarios requires the development of a communication interface with the verification platform. Furthermore, since UVM verification platforms cannot dynamically instantiate such static simulation models, embedding them into a UVM environment prevents the utilization of UVM's powerful class library ecosystem. To address the issues mentioned above, this paper employs the UVM standard class library, which leverages the object-oriented features of SystemVerilog, to construct a simulation model of peripheral chips. This simulation model is then embedded into the UVM verification platform. Experimental results demonstrate that the verification platform can dynamically configure the operating modes of the simulation model during runtime. In other words, the model is capable of simulating scenarios that involve switching between multiple operating modes of peripheral chips, thereby enriching the verification scenarios for FPGA software. The chip simulation model proposed in this paper, based on the UVM standard class library and integrated with the UVM verification platform, reduces to some extent the simulation complexity of peripheral chip multi-mode switching scenarios and alleviates the development and maintenance difficulties associated with simulation models for peripherals featuring multiple operating modes. This approach provides a new and feasible solution for developing simulation models in the verification of FPGA software related to interface timing control.

To address the problem of cross-scene object tracking, this paper proposes a scene transformation-based algorithm for stable object tracking. By integrating a feature enhancement module and an object refinement module into the Kernelized Correlation Filter (KCF) algorithm, the contour and detailed information of the target are highlighted. Meanwhile, the U-Net neural network is introduced to achieve accurate detection of scene boundaries, and a dynamic update and target recapture strategy is incorporated into the decision-making framework to ensure stable object tracking.Given that the proposed algorithm fails to meet real-time performance requirements due to increased computational complexity, the Atlas 300I edge computing module is adopted for algorithm acceleration. This approach effectively balances the trade-off between algorithm complexity and tracking performance, improving tracking accuracy while satisfying the real-time constraints of practical engineering applications. Experimental results demonstrate that the proposed algorithm can effectively resolve the issue of tracking drift in cross-scene object tracking scenarios, providing valuable insights for future research in this field.

To address the demand for miniaturized, and low-power Synthetic Aperture Radar (SAR) systems in unmanned platforms, this study developed a high-speed imaging micro-system leveraging heterogeneous System-in-Package (SiP) technology. The system integrates an FPGA, a DSP, multiple DDR3 memory chips, and a LDO. Comprehensive electrical, thermal, and mechanical simulations validated the system’s signal integrity, thermal management, and structural robustness. Electrical simulations confirmed that key signals of DDR3-1600MT/s and 5 GT/s SerDes meet design requirements in terms of insertion loss, return loss, and crosstalk. Thermal simulations verified that the junction temperature of chips remains controllable with the application of a cold plate. Mechanical analysis demonstrated that the stress under thermal cycling and vibration shock conditions remains below the material limits. Imaging experiments showed close agreement between point-target responses, real-world data, and MATLAB simulations, with key metrics such as Peak Side Lobe Ratio (PSLR) meeting performance targets. These results demonstrate the micro-system’s viability for enabling lightweight, high-performance SAR processing in unmanned platforms.

针对无缆式光伏面板清扫机器人在无市电场景下续航时间短、维护频繁的问题，本文设计了一种基于硬件与软件协同优化的低功耗嵌入式系统。系统以超低功耗微控制器STM32L496为核心，构建了包含高效DC-DC转换器与低静态电流LDO的分级电源管理电路，为通信、传感器等外围模块设计了软件可控的独立电源开关，并对强电伺服系统的工况自适应进行低功耗优化。在FreeRTOS上实现了基于实时时钟（RTC）的定时唤醒机制与动态功耗管理策略，使系统在非作业时段可进入微安级深度休眠状态。理论建模与分析表明：与未低功耗优化的方案相比，本系统在典型工作周期下的平均功耗降低约82.2%，搭载10000mAh锂电池的机器人理论续航时间从7.2天延长至40.5天，显著提升了其持续作业能力与运维经济性。

Addressing the challenges of heavy maintenance tasks, difficult physical layer fault localization, and high communication latency associated with traditional "FPGA+ARM" dual-chip architectures in current Multifunctional Vehicle Bus (MVB) networks, this paper designs an MVB bus waveform acquisition and fault diagnosis system based on the ZYNQ heterogeneous SoC platform. First, leveraging the on-chip high-bandwidth interconnection characteristics of the PL (Programmable Logic) and PS (Processing System) in the ZYNQ architecture, a hardware-software co-design acquisition architecture is constructed, resolving the timing bottleneck of cross-chip transmission. Second, for common short-circuit, open-circuit, and impedance mismatch faults in the MVB physical link, a diagnosis method combining key time-domain feature extraction and an expert rule base is proposed. Decision thresholds are set based on the IEC 61375 standard and statistical criteria, replacing traditional single-threshold judgment. Finally, a semi-physical simulation experimental platform was built for system verification. Test results show that the system can accurately reconstruct high-speed MVB signal waveforms; in a laboratory environment, the end-to-end delay from acquisition to diagnosis is controlled at the millisecond level, and typical physical layer faults can be accurately diagnosed. This design achieves deep on-chip coupling of data acquisition and intelligent processing, providing a highly integrated engineering solution for train network status monitoring.

To address the data stream conversion problem between serial input and parallel output of four LCoS zones in 8K LCoS drivers for high-definition multimedia interfaces, and to meet the high-performance driving requirements of ultra-high-definition displays, this paper studies a frame buffer module based on DDR SDRAM. Developed using Verilog HDL, the control logic is constructed using the AXI bus protocol and FDMA IP core. A FIFO buffer is configured to handle asynchronous clock domain data transfer. Address partitioning enables independent read/write operations across the four zones, address control facilitates vertical image flipping, and a synchronization signal module adapts to the output timing of 8K LCoS. Results show that this module can stably buffer data at a resolution of 7680×4320, supports ≥3 frames pre-stored, and achieves the conversion from serial data to parallel output across four zones.

针对在真空强电磁干扰环境下，微弱推力测量信号易被噪声淹没而导致测量精度低、动态响应差的问题，本文提出一种基于卡尔曼滤波与电磁屏蔽相结合的信号降噪优化方案。该方案通过构建多层复合电磁屏蔽系统，从物理层面抑制空间辐射干扰；同时，建立测力计系统的动力学模型，并应用卡尔曼滤波算法对采集信号进行最优状态估计，以分离确定性推力信号与随机过程噪声和测量噪声。实验结果表明，该方案能够将信噪比（SNR）提升近30dB，与传统低通滤波相比，在有效抑制噪声的同时，显著改善了系统的动态响应特性，为高精度、高动态范围的微推力测量提供了可靠的技术途径。

This paper presents the design of a high-speed real-time signal processing radar digital front-end based on Xilinx FPGA.The FPGA in this radar front-end fully utilizes its abundant resources, including logic, RAM,DSP, and high-speed interfaces, to implement functional modules such as 10-Gigabit Ethernet, Microblaze, and high-speed cache. This enables the FPGA to perform control, preprocessing, and high-speed data transmission, resulting in a radar processing front-end with a simple hardware structure, high signal processing capability, and fast data transmission speed. In software implementation, the high-speed data read-write timing is meticulously designed according to radar waveform characteristics to meet the data transmission capacity requirements. It has been successfully applied in real-time processing for surveillance radar projects, achieving excellent results

A two-stage operational amplifier with low input bias current, rail-to-rail input, high gain, and high bandwidth has been designed by combining a folded-cascode first stage with a class-AB output stage, incorporating a linear transconductance (Gm) loop and gain-boosting techniques. The first stage employs a folded-cascode architecture, achieving rail-to-rail input through parallel NMOS and PMOS input differential pairs. A dedicated current compensation scheme ensures a constant output impedance of the first stage. The second stage utilizes a class-AB output configuration, where a translinear loop precisely sets the quiescent current of the output stage, resulting in improved drive capability and reduced power consumption. Gain-boosting techniques are applied to further enhance the output impedance of the cascode structure, thereby increasing the overall DC gain. The op-amp is fabricated in a SMIC 180nm MS BCD CMOS process.After tape-out, a test platform was independently developed by designing the test circuitry and fabricating a custom PCB board. Key parameters of a broadband low-input-bias-current operational amplifier, including input bias current, offset voltage, open-loop gain, small-signal bandwidth, slew rate, and noise, were measured using an oscilloscope, network analyzer, and spectrum analyzer. Test results demonstrate that with a 2pF load capacitor, the amplifier achieves a low-frequency gain of 50dB and a gain-bandwidth product (GBW) of 380MHz.