In light of the urgent demand for system-level health management in the domestic application of the current VPX architecture within high-reliability fields such as aerospace and defense electronics, this paper proposes and designs a domestic health management module based on the collaborative architecture of Phytium processor, FPGA and MCU, and deeply integrates it into the VPX system framework to achieve comprehensive, intelligent, and full-life-cycle monitoring and management of the system operating status. Based on the VITA46 specification and IPMI protocol, the health management module establishes a three-level collaborative, clearly divided, and mutually redundant core control architecture of "Phytium Processor + FPGA + MCU" through the collaboration of three core units, which significantly improves system reliability and fault tolerance, and reduces operation and maintenance costs. The Phytium D2000/8 undertakes system-level health status decision-making, data fusion processing, and global scheduling; the FPGA, as the acceleration control unit, is responsible for high-speed data acquisition, precise timing control, and custom interface expansion;the MCU focuses on real-time collection of key parameters such as voltage and temperature, local fault early warning, IPMI bus, and Ethernet communication. The module integrates domestic sensors, communication interfaces, and protocols, and realizes health management functions such as status monitoring, fault diagnosis, and fault prediction of key components in the VPX system through software-hardware collaboration. Through modular design, standardized interfaces, and custom protocols, the module can be seamlessly embedded into existing VPX systems, improving system operation and maintenance efficiency and localization rate. This solution fully adopts localized components and technical routes, has independent intellectual property rights, meets the requirements of the national independent and controllable strategy, and provides a replicable and promotable technical paradigm for the localization, intelligence, and sustainable operation and maintenance of high-performance embedded systems under the VPX architecture. Experimental and application results show that the health management module exhibits high reliability and accurate monitoring capability in harsh environments, and has significant application value.

An ASIP (Application-Specific Instruction-set Processor) acceleration core based on RISC-V is designed specifically for Spiking Neural Networks (SNNs). The goal is to provide flexible and efficient neuronal computation support for various low-power applications, offering a new approach for neuromorphic chip computation cores. An in-depth analysis of the parallel computation patterns of SNNs reveals their computational modes, leading to the introduction of operational instructions and extension modules to accelerate state parallel computation. SIMD (Single Instruction, Multiple Data) operations enhance parallel computation efficiency, allowing the core to process multiple neurons or synapses simultaneously. To further boost efficiency, fixed-point computation modules, and vector multipliers are incorporated, significantly increasing SNN operation speed with minimal precision loss. Specialized extension instructions for the Izhikevich (IZH) and Leaky Integrate-and-Fire (LIF) neuron models provide direct computational support for specific neuron models, enhancing efficiency. Performance evaluation across five application scenarios shows that the ASIP computation core significantly improves parallel state processing while maintaining SNN performance.

本文针对视频编码中离散余弦变换（DCT）在处理非平稳残差信号时性能下降的问题，提出一种基于可逆结构扰动的频域变换优化方法。该方法在不改变标准DCT变换基本身的前提下，通过一组可逆的行循环移位操作对预测残差进行预处理，调整其空间统计分布，使其更接近DCT的最优工作区间，从而提升变换编码效率。算法通过编码单元（CU）宽高动态计算偏移量，采用率失真优化机制自适应选择最优扰动模式（含无扰动模式），以极低开销将模式标识写入码流；在解码端通过对应逆扰动实现残差无损重建。基于JCT‑VC标准Class B的三组全高清测试序列的实验结果表明：所提方法在混合各类CU尺寸与预测模式的整体测试中，可实现约1.91%的码率降低；尤其在帧间预测模式及大尺寸CU上优势显著，其中ParkScene序列4096像素CU上取得2.80%的码率降低，算法增益随CU面积呈现“两端高、中间低”的U型特征。该方法在保持与标准DCT相近计算复杂度的同时，有效提升了压缩性能，为视频编码变换模块的硬件友好型优化提供了新思路。

With the rapid development of edge Artificial Intelligence (AI) technologies, resource-constrained terminals impose increasingly stringent requirements on the energy efficiency of neural network inference. However, existing multi-bit neural network models and their hardware implementations generally suffer from high power consumption and complex architectures, which limit their applica-bility in low-power scenarios. Therefore, this work focuses on the demand for lightweight inference in edge vision tasks and propos-es a low-power computing-in-memory (CIM) circuit design method for convolutional inference based on Binarized Neural Networks (BNNs).Based on the charge-domain coupling principle, a compact 10T1C-SRAM CIM cell is designed. To accommodate the ana-log output characteristics, a low-offset comparator and an efficient input driver circuit are further developed. In the proposed archi-tecture, three convolutional layers (Conv2–Conv4) of a five-layer BNN are mapped onto the CIM array to accelerate convolution operations in BNN inference. Meanwhile, to avoid frequent off-chip memory accesses during multi-layer convolution processing, a sliding-window-driven data scheduling mechanism is adopted to complete the inference process. The proposed architecture is im-plemented using the TSMC 180-nm CMOS process. The system achieves an average power consumption of 38.67 μ W and an aver-age energy efficiency of 243 TOPS/W, outperforming several existing low-power CIM architectures. The system enables the infer-ence of a three-layer Convolutional Neural Network (CNN) under microwatt-level power consumption, demonstrating significant energy-efficiency advantages.

In the toner cartridge chip of a laser printer, the 32-bit data processed by the RF front-end and ADC requires encryption to ensure the security of data transmission and storage. Addressing challenges such as limited hardware resources, significant critical path delays, and constrained throughput in the drum chip, this paper adopts FPGA as the hardware prototype verification platform and introduces resource constraints during the comprehensive implementation process to simulate the implementation effect under embedded-level gate circuit resource conditions. Collaborative optimization focuses on three key modules: data padding, message expansion, and compression functions. A pipeline-based dynamic padding structure driven by finite state machines replaces traditional serial padding logic. a sliding-window pipeline based on shift registers to achieve temporal overlap between message expansion and compression operations; and a 4:2 compressor structure within the compression function's critical path, reconfiguring multi-operand accumulation logic to reduce critical path latency and decrease clock cycles per compression operation. Test results demonstrate that this design has been validated on Xilinx Zynq-7000 series FPGAs, achieving a throughput of 35.56 Gb/s at a maximum operating frequency of 139 MHz, with hardware resource utilization of 1492 Slices. Compared to similar approaches, this solution achieves a superior trade-off between throughput and resource overhead, making it suitable for resource-constrained applications demanding both performance and resource efficiency.

To address the low efficiency and high false positive rates of traditional SSI absolute encoder testing, this paper presents an FPGA-based automated defect detection system. The system adopts a dual-processor architecture, integrating an FPGA and an STM32 microcontroller. The FPGA performs SSI communication parsing, data acquisition, and real-time detection of anomalies such as skipping, looping, and dead codes, while the STM32 handles stepper motor control and user interaction. An adaptive threshold algorithm based on encoder increments, combined with cache logic, enables accurate and timely analysis of encoder outputs. Experimental results demonstrate that the system achieves over 99% detection accuracy even at a communication rate of 2 MHz, exhibiting strong resistance to interference and compatibility with multiple encoder types. The proposed system offers a cost-effective, high-performance solution for efficient and reliable encoder inspection and quality control in industrial applications.

To address the high cost and extended downtime of manual maintenance for aerospace sealed-cabin equipment, this paper proposes a reliable over-the-air (OTA) upgrade solution. The method adopts a dual-image backup mechanism with integrity verification and adaptive network protocols, enabling secure firmware updates of up to 16 MB and automatic rollback in case of failure. Experimental results show a misdetection probability below 9.32×10-10, approximately doubles the Flash lifespan, a 99.9% upgrade success rate, and 100% fault recovery. Compared to traditional manual methods, this approach reduces maintenance time from hours to about one minute and cuts costs by over 90%, effectively resolving key maintenance challenges.

To address the issues of heavy reliance on manual operations, low efficiency, and insufficient consistency during on-site verification of dial pressure gauges, this paper designs and implements a novel portable automated verification system based on deep learning. This system employs a hierarchical collaborative architecture comprising ‘object detection-character recognition-geometric calculation-process management’. Compliant with JJG 52-2013 regulations, the system centres on an embedded platform integrating an autofocus camera, LED ring light, micro-electromagnet tapping device, and process guidance module. This enables localised model deployment and standalone operation without network connectivity. To address misidentification and confusion in dial information recognition, a general lightweight OCR model underwent targeted fine-tuning. An Information Correction Algorithm (ICA) was designed, combining regular expression filtering with arithmetic sequence fitting to achieve consistent verification and correction of scale values. Addressing the unique demands of pointer reading tasks, an enhanced YOLO11n-PR lightweight object detection network was proposed to improve pointer keypoint localisation accuracy, thereby enhancing reading precision in complex industrial environments. Experimental results demonstrate that compared to the baseline model, dial information recognition accuracy improves to 97.44%, word error rate (WER) decreases to 2.56%, and character error rate (CER) reduces to 1.28%, enabling precise differentiation between morphologically similar numerals and symbols. The Mean Absolute Error (MAE) and Root Mean Square Error (RMSE) for pointer readings decreased from 0.0421 and 0.0474 to 0.0154 and 0.0270 respectively, representing reductions of 63.42% and 43.04%. The average calibration time per gauge was reduced to 73 seconds, achieving approximately fourfold efficiency gains over standard manual operations. The system demonstrated stable and reliable performance during prolonged continuous operation, indicating strong engineering applicability and practical value for field deployment.

In SoC (System on Chip) systems containing DDR memory, the CPU accesses DDR extensively. When the CPU performs read/write operations with short burst lengths, mixed read/write commands, or non‑continuous addresses, the read/write efficiency of DDR decreases sharply. The CPU must wait for DDR read/write operations to complete before proceeding with other tasks, which significantly degrades CPU efficiency. Based on the existing DMA (Direct Memory Access), this design adds the following functions:(1) Support for the AXI4 interface to DDR;(2) Support for burst lengths of 1/2/4/8/16/32/64/128/256;(3) Support for CPU-initiated pause, stop, and start operations during DMA execution;(4) An internal DMA error status detection mechanism that generates an interrupt to report errors to the CPU. This design mainly uses the newly added functions to support CPU read/write access to DDR under different scenarios. When the CPU reads/writes DDR at continuous addresses, an appropriate burst length can be selected according to the data length. When the CPU reads/writes DDR at non‑continuous addresses, the burst length is set to 1, and the DMA continuously sends data with a burst length of 1 internally to complete the read/write operations for non‑continuous addresses. This design uses the Xilinx K7-325T FPGA as the hardware platform, with joint verification using Vivado and VCS. Simulation and board-level experiments verify the correctness of DDR DMA read/write operations for data with burst lengths of 1/2/4/8/16/32/64/128/256.Bandwidth under different burst lengths is measured using the 4‑Gb DDR3 device MT41J256M16xx-125 which is as expected.

The reliance on commercial EDA tools and the complexity of environment construction in traditional processor verification workflows often hinder agile development. To overcome these bottlenecks, this paper presents an agile, core-level verification methodology for RISC-V processors driven entirely by an open-source toolchain. By leveraging Verilator as the simulation engine and the Python-based Cocotb framework's coroutine mechanism, the proposed approach achieves both high-level abstraction of test stimuli and precise cycle-level driving. Furthermore, a lightweight test architecture is designed to accelerate the feedback loop. Case studies on the open-source RISC-V Ibex core demonstrate that, compared to the traditional Universal Verification Methodology (UVM), this scheme reduces code size by approximately 85% and compresses the iteration cycle of a single test case from hours to minutes—all while ensuring the effective verification of critical paths such as instruction execution and exception response. This solution significantly enhances early-stage design efficiency and offers a cost-effective alternative for educational experiments and prototype development.

In the off-chip interconnection application scenario of domestic embedded system, the traditional interconnection interfaces have many bottleneck problems such as insufficient bandwidth, high latency, large CPU load, which are increasingly unable to meet the high-speed data transmission needs of key fields such as aerospace and military. RapidIO, as a special interconnection bus protocol for embedded systems, has the advantages of high bandwidth, low latency and flexible topology. To solve the above problems, this paper proposes a serial interface software and hardware optimization design scheme based on RapidIO V2.2 protocol for domestic embedded processors. In terms of hardware design, a 4-channel 6.25 Gbaud integrated architecture is designed, which integrates 2 independent Write/Read DMA channels and implements a linked-list DMA transmission mechanism. By pre configuring the linked list descriptor, batch transmission of discontinuous address data can be completed by a single DMA trigger. At the same time, the hardware cache consistency bus is designed based on MOESI protocol to solve the pain point problem that the software synchronization cache takes too long after DMA transmission in the application. In terms of software implementation, the RapidIO driver is optimized and improved based on hardware characteristics, and the number of data copies in the application is reduced through shared memory and memory mapping mechanism based on zero copy technology, so as to further improve the data transmission rate. Verified by actual chip tests, the read and write rates of the RapidIO interface bus reach 2145.92 MB/s and 1876.35 MB/s respectively, which reach more than 80% of the theoretical bandwidth of 6.25 gbaud in four channels. And in the actual application project, the optimized data transmission rate was increased from 630 MB/s to 1463 MB/s, and the CPU load was reduced by 32%. The scheme meets the requirements of the off chip interconnection performance of the domestic embedded system, and provides reliable technical support and application examples for the high-speed interconnection of the domestic SOC.

Serial communication is widely utilized in industrial control, the Internet of Things, and embedded systems. Asynchronous protocols such as UART are limited by low transmission rates and strict clock tolerance requirements, whereas synchronous protocols like SPI necessitate an additional clock signal, incurring inherent disadvantages in power consumption and cost. An asynchronous serial communication method based on level width modulation is proposed, where symbols are encoded by the duration of a level and symbol synchronization is achieved via signal edges. This method can be implemented using purely digital circuits, enabling high clock tolerance communication over a single-wire connection. By optimizing parameters such as the transmitted level width and the receiver decision window, flexible trade-offs among communication rate, clock tolerance, and SNR-FER performance are enabled. The mathematical relationship between the parameter set and clock tolerance is derived and subsequently verified through simulation. The simulations of SNR-FER curves for typical parameter sets under different operating modes were obtained. A purely digital transceiver prototype was implemented on an FPGA with a clock frequency ratio of 1.2 between transceivers, a frame error rate of 2.4×10⁻⁷ and an average data rate of 142.6 Mbps are achieved at an SNR of 19.4 dB. This method is well-suited for on-chip clock domain crossing or off-chip low-power communication scenarios, particularly where a significant clock frequency difference exists between transceivers and wiring resources are constrained, meeting the demands for medium-rate, low-cost communication.

An all-digital phase-locked loop(ADPLL)designed for CMOS image sensor chips.A dual-loop all-digital phase-locked loop based on injection-locked technology is designed to address the issue that traditional ADPLL rely on high-precision time-to-digital converters(TDC),making them difficult to implement through a fully digital design flow.This ADPLL does not depend on highly customized modules;instead,it leverages injection locking,PVT sensing compensation,and dual-loop techniques to enhance phase noise performance.As a result,all modules of the PLL,including the digitally controlled oscillator(DCO),can be implemented using standard cells and Verilog code.The design can be fully realized through a digital flow,fully leveraging the high portability advantages of all-digital PLL.In addition,to address the issue of potentially long locking times caused by the need for multiple phases to achieve lock in this PLL,this design incorporates a lock detection and frequency prediction algorithm to improve the locking speed.

This paper presents a bandwidth and resolution-configurable discrete-time Delta-Sigma modulator based on switched-capacitor circuits. To address the diverse requirements for measurement precision, signal bandwidth, and dynamic range in various industrial applications, the modulator features a reconfigurable loop filter architecture that can switch between third-order and fourth-order modes via an external control signal; concurrently, the system enables the collaborative adjustment of signal bandwidth and resolution by adapting different oversampling ratios (OSRs). System modeling and simulations were conducted using MATLAB (OSR=200). Regarding stability, the third-order mode exhibits more relaxed stability conditions with a Maximum Stable Amplitude (MSA) of -4.4 dBFS—an optimization of 15.2 dB over the fourth-order mode (-19.6 dBFS)—making it suitable for large-amplitude signal processing. In terms of resolution, the fourth-order mode demonstrates superior noise-shaping capabilities, achieving a dynamic range (DR) of -154.4 dBFS, which is a 24.8 dB improvement over the third-order mode (-129.6 dBFS), allowing for the precise resolution of weak signals. To verify the configurability of bandwidth and precision, performance metrics were tested under varying OSRs. Simulation data indicate that in the low-OSR region (OSR < 20), the third-order modulator provides a superior Signal-to-Quantization-Noise Ratio (SQNR); for instance, at OSR=14, the third-order and fourth-order modes yield SQNRs of 22.549 dB and 15.383 dB, respectively. As the OSR increases (OSR ≥ 20), the fourth-order mode's noise-shaping advantage becomes dominant. This design not only overcomes the limitations of single-structure modulators in multi-scenario applications but also achieves an optimized bandwidth-precision trade-off by leveraging the higher gain of the third-order structure at low OSRs and the high-precision characteristics of the fourth-order structure at high OSRs, effectively resolving the stability issues of high-order modulators under large-signal conditions.

This paper presents a wideband low-phase-noise voltage-controlled oscillator (VCO) implemented in a 22 nm CMOS advanced process for high-performance frequency synthesis systems requiring both wide tuning range and low phase noise. The proposed VCO adopts a complementary cross-coupled topology and incorporates a transformer-coupled common-mode noise-suppression network at the sources, which establishes a high impedance at the second harmonic to suppress flicker-noise upconversion and improve oscillation waveform symmetry. In addition, a 3-bit programmable source capacitance is introduced for adaptive phase-noise optimization. To alleviate the inherent tradeoff between wide frequency coverage and low VCO gain, a hybrid tuning scheme combining 10-bit switched-capacitor coarse tuning with varactor-based fine tuning is employed. Operating from a 1.2 Vsupply, the proposed VCO consumes 3.35 mW and occupies an area of 0.185 mm². It achieves a continuous tuning range of 6.07–8.50 GHz and exhibits a phase noise of −122.1 to −120.6 dBc/Hz at a 1-MHz offset frequency.

Addressing the capacitor mismatch issue in high-precision successive approximation analog-to-digital converters (ADCs), this paper designs a foreground calibration technique based on sine signal input. By collecting kernel data for multiple fitting to ensure the signal-to-noise ratio (SNR) meets the specifications, the capacitor mismatch register values are obtained and OTP programming is performed. This effectively improves conversion accuracy and SNR without affecting the ADC sampling rate. This foreground calibration technique is derived from the Least Mean Squares (LMS) algorithm. It collects 16K kernel data from the SAR ADC and performs nonlinear least squares fitting using Matlab. Drawing on the idea of the LMS algorithm, the residual signal undergoes multiple iterations, with each iteration adjusting the weight of each bit of the ADC accordingly. After approximately 1000 iterations, the SNR reaches 88 dB and the spurious-free dynamic range (SFDR) is 98 dB, which are 22 dB and 17 dB higher than before calibration, respectively. Simulation and test results show that this calibration technique effectively enhances the output performance of the ADC.

Irregular data access patterns in high-performance computing and intelligent computing often render traditional data prefetching techniques ineffective. Existing models that rely on fixed rules or offline learning based on specific program contexts also struggle to adapt to dynamically changing memory access patterns during runtime. While the Pythia reinforcement learning (RL) prefetching framework demonstrates adaptability through online learning, it still requires manual tuning under extreme irregular workloads, limiting its generalization in practical applications. This paper proposes IEP(Irregular Enhanced Pythia), a context-aware reinforcement learning prefetching framework to enhance the prediction capability for irregular memory access patterns. The framework introduces two key innovations: first, an irregular feature enhancement module that incorporates address bit masks and access sequence distance as state features to capture hidden spatiotemporal patterns in memory allocator behavior, thereby improving the representation of irregular memory accesses; second, a hierarchical reward strategy module that employs a dynamic reward mechanism combining confidence awareness and bandwidth sensitivity to finely guide the learning process of the agent, accelerating policy optimization and improving final performance. Experiments were conducted using the ChampSim simulator, testing various irregular workloads. Results show that compared to the Pythia framework, the proposed solution achieves a maximum improvement of 2.27% in average prefetching accuracy and 2.90% in average single-core IPC for typical irregular workloads such as Ligra and PARSEC, while maintaining stable performance advantages in multi-core environments.

To assist visually impaired individuals in navigation, an AI-based machine vision system for collecting tactile paving information has been designed to enable intelligent data acquisition. The system identifies standard tactile paving through image edge detection and morphological constraints, enabling wheeled robots to autonomously traverse tactile paths. It employs the YOLOv8 object detection model paired with Huawei Ascend AI processors to detect anomalies in tactile paving, transmitting detection results to a host computer via Wi-Fi. During testing, simulated tactile paving tiles measuring 30cm × 30cm were laid out. Multiple detection runs were conducted with damaged tactile paving, missing sections, and both movable and immovable obstacles placed at various positions. Testing confirmed the system's capability to collect tactile paving data within defined scenarios, identify anomaly types and locations, with an average detection accuracy of 95%. The average absolute error in anomaly location pinpointing was less than 9.12 cm relative to actual positions. This system can assist municipal authorities in understanding tactile paving conditions and support safe travel for visually impaired individuals.

Abstract: To address the predictability issue of interrupt latency in real-time operating systems (RTOS) under multi-core heterogeneous architectures, this paper proposes a layered interrupt latency modeling method and a comprehensive benchmark testing framework, using the domestic RK3588 chip and SylixOS real-time operating system as research subjects. Theoretical modeling is employed to analyze the impact of hardware architecture and operating system scheduling strategies on interrupt response time, and a testing scheme incorporating multiple scenarios such as single-core idle, mixed load, and full-core high pressure is designed. The 'modeling-testing-optimization' methodology is proposed, providing a systematic reference for real-time evaluation and optimization of multi-core heterogeneous platforms.

To address the challenges of stability assessment caused by the change in the center of gravity after the renewal of ship equipment, as well as the problems of high cost, long time consumption and difficulty in popularization of traditional inclining tests on small and medium-sized fishing, an automatic ship stability measurement system based on embedded technology is designed. The system takes an inertial measurement unit (IMU) as the core sensing module, and realizes high-precision measurement of ship roll attitude angle and rapid calculation of metacentric position through multi-source attitude data acquisition, embedded real-time processing and wireless transmission. Adopting a master-slave architecture and with the STM32F401 microcontroller as the core, the system integrates an accelerometer and an ultrasonic ranging module, and transmits data to the upper computer via 2.4GHz communication to achieve multi-dimensional perception of the dynamic response of the ship under slight inclination. In the outdoor model ship test environment, the system significantly simplifies the measurement procedure through an automated process. Compared with the traditional manual calculation and observation, the single measurement time is greatly reduced. The average relative error of metacentric height measurement is less than 3%, which verifies the high efficiency of the system in data acquisition and algorithm solving. This system provides an efficient, cost-effective and field-operable solution for the stability safety assessment of fishing vessels after equipment renewal, meeting the demand for rapid on-site measurement in marine engineering.