This paper introduces a clock system based on MCU, including the components and advantages and disadvantages of the clock system. A clock architecture suitable for automotive electronic MCU is proposed, and the overall design framework is given. The working principle of the system and the relationship between the system clock and power consumption are analyzed in detail, and the clock design related to functional safety is described. Under the 40nm process library for rail technology, the circuit was simulated using soft tool and implemented and applied in the CKS32K1XX chip project.

Due to the high incidence risk of neonatal jaundice and the limitations of conventional monitoring methods, there is a clinical need for non-invasive dynamic jaundice detection devices. This study designed a wearable system for dynamic jaundice level and physiological parameter detection. The system includes a forehead-mounted wireless physiological signal collector, a Bluetooth communication host and a data analysis platform based on LabVIEW. The system uses the highly integrated MAX86916 optical sensor to synchronously collect four-channel photoplethysmography (PPG) signals, and obtains bilirubin, heart rate, and blood oxygen saturation data through signal processing. The nRF52832 microcontroller with Bluetooth Low Energy (BLE) protocol is used for wireless communication. The data is transmitted wirelessly to the Bluetooth communication host, and then uploaded to the LabVIEW program of the PC via USB for display and storage. To verify the functionality and performance of the system, basic parameter tests, and comparative tests of each physiological parameter with commercial instruments were conducted in sequence. The device (13.5g, 41mm×29.7mm×15.1mm) can monitor continuously for 5 hours. The detection range of the bilirubin prediction model is 1~13mg/dL. Measurements demonstrated bilirubin, heart rate and blood oxygen were in strong agreement with standard instruments (p>0.05). And the maximum absolute errors for bilirubin, HR, and SpO₂ measurements were 0.97mg/dL, 1bpm, and 2.1%, respectively. Moreover, the system can sensitively track the decrease in heart rate after exercise and the changes in blood oxygen during breath-holding. The system demonstrates accurate monitoring of jaundice, heart rate, and blood oxygen levels. It integrates the advantages of lightweight design, wearability, multi-parametric detection, and non-invasive dynamic measurement capabilities. After further optimization, it is expected to be applied in neonatal clinical monitoring.

Compared to custom-designed chips, Field Programmable Gate Arrays (FPGAs) support flexible hardware reconfiguration and offer advantages such as shorter design cycles and lower development costs. They are widely used in fields such as communications, data centers, radar, and aerospace. The design goal of FPGA architectures is to create highly programmable FPGA chips while minimizing the area and performance costs associated with reconfigurability. With the continuous evolution of application demands and process technology capabilities, FPGA architecture design is entering a new phase. This article briefly describes the basic architecture of FPGA and FPGA architecture evaluation, summarizes the latest developments in new FPGA architectures and circuit design technologies, and discusses the technical challenges and development trends of new FPGA architectures and circuit design.

A compact model of Fully Depleted Silicon-on-Insulator （FDSOI） based single transistor pixel sensor （1T-PS） affected by total ionizing dose （TID） effects is investigated, which considers the generation of fixed charges within the buried oxygen （BOX） layer and interface states at the surface below BOX. The corresponding relationship between irradiation dose and threshold voltage degradation of 1T-PS can be obtained through this model. By integrating the model into BSIM-IMG and executing the typical image input layer of an artificial neural network, the impact of the TID effects on the accuracy of 1T-PS arrays performing vector matrix multiplication （VMM） is studied. The results indicate that after exposure to a total ionizing dose of 600 krad（Si）, the recognition accuracy decreases to approximately 85%.

To enhance the real-time performance, scalability, and reliability of CT detector nodes, and to meet the bus communication requirements of the current slip ring equipment, a CT detector CANopen node design method is proposed. This method involves hardware node design using the XMC4000 series microcontroller to build the hardware platform, as well as adaptation of hardware drivers and a real-time operating system. A customized object dictionary is designed to include command control and status feedback. By optimizing the state machine and message task flow, task real-time performance is improved.Test results show that the functionality complies with the CANopen protocol specifications, and the electrical characteristics meet the requirements for voltage, edge transition, and bit width testing. Additionally, under continuous transmission of 5,156 frames, the success rate reaches 100%, demonstrating high reliability. The bus delay does not exceed 480ns, ensuring excellent real-time performance. The designed object dictionary can be reused and transplanted in CT systems with different hardware platforms, effectively supplementing the current medical device configuration file (CiA-412).

Aiming at the problem of data noise interference in the monitoring of bridge bearing inclination and stress, a real-time monitoring data preprocessing system based on Kalman filter is designed in this paper. The system uses classical Kalman filtering algorithm to preprocess the tilt angle and stress data collected by the sensor, which effectively suppresses the noise interference. Based on the parallel computing advantage of FPGA, the functions of data acquisition, filtering and transmission are realized, and the monitoring data of bridge bearings are dynamically displayed in real time combined with the upper computer. The experimental results show that the signal-to-noise ratio (SNR) of the filtered stress signal is 32.10 dB, the mean square error (MSE) is 0.0518, the correlation coefficient is 0.5811, and the variance ratio is 0.7018; The SNR, MSE, correlation coefficient and variance ratio of inclination signal after filtering are 33.98 dB, 0.0418, 0.07032 and 0.6291, respectively, indicating that the filtering algorithm can effectively suppress noise interference. The system is stable and reliable, can achieve rapid data processing ability, and can meet the needs of real-time monitoring of bridge bearing inclination and stress. At the same time, this paper uses ASIC process to design the Kalman filter algorithm chip, and realizes the Kalman filter circuit based on 180nm CMOS process. The clock frequency is 160MHz, and the comprehensive area is 599131um ².

Based on HKN201 of Xiangteng Micro as the core, a strongly real-time, highly concurrent and high-performance edge-end embedded intelligent computing system has been constructed. Combining the design concept of high-speed circuits and practical engineering applications, the basic design methods and effective control measures for power integrity and signal integrity are provided, and simulation analysis is carried out with simulation results given. Finally, application tests are conducted on this system and performance indicators are presented. The experimental results show that this scheme has the characteristics of being universal, highly scalable and highly reliable, providing references for the research on intelligent products

High-speed SerDes rates have progressed from 56Gbps to 112Gbps and beyond. Preserving signal integrity at these ultra-high speeds while balancing power consumption, reliability, flexibility, and cost-effectiveness is a hot topic in current research. The latest research progress in key technologies related to 112G SerDes is deeply explored from four aspects—transmitter, receiver, clock structure, and low-power techniques—based on the current mainstream architecture of analog-to-digital conversion and digital signal processing. This exploration is provided as a reference for research related to high-speed SerDes technology.