This article focuses on the site selection problem for high-speed railway stations. By collecting information from multiple high-speed railway stations, mathematical models are established using MATLAB, SPSS, Excel software, and incorporating theories of mathematical statistics and intelligent algorithms. An evaluation system for site selection criteria is established, including factors such as distance from the city center, distance from the airport, passenger flow, and others. The BP neural network algorithm is applied to calculate the comprehensive evaluation matrix. By comparing the success and failure cases of Guangzhou South and Shenyang South, the accuracy of the model results is confirmed. This article also explores the specific implementation of high-speed railway station site selection. Taking the Dan-Jing of the high-speed railway as an example, the article successfully determines the site selection location by establishing an objective function of minimizing economic costs and relevant constraints. Considering the convenience of passenger travel and construction costs in high-speed railway station site selection, the optimal coordinates and the minimum total cost are obtained through genetic algorithm. The mathematical model proposed in this article has the characteristics of objectivity, accuracy, and strong practicality.

A high-precision positioning watch based on intrinsic safety was designed and implemented to address the issues of portable positioning tags placed at the waist in coal mines, which are difficult to seek help in emergency situations, lack of LCD display of escape route information, and difficulty in perceiving vibrations. The battery output of the watch adopts a three-level protection to achieve a higher safety level. The heart rate monitoring sensor is used to collect the heart rate status of workers entering the well in real-time, monitor their physical health status. UWB positioning technology and tunnel base station are used for real-time distance measurement, and the positioning accuracy is improved from meter level to centimeter level. Through UWB communication network, the watch can achieve two-way communication with the ground dispatch room. In emergency situations, one click underground rescue is required, and when gas exceeds the limit, evacuation information is received from the ground. The LCD displays the escape route information. At the same time, the watch has multifunctional alarm prompts such as sound, light, and vibration, providing more powerful protection for safe underground operations of miners.

In this paper, a software upgrade system for communication power controller is studied. The system is developed based on the GD32F405RG chip, and the RS485 communication bus is used as the information transmission mode to receive the upgrade program in the APP stage, and then the correctness of the information transmission is verified by verification algorithms such as CRC, and then the upgrade program is stored in the off-chip memory chip W25Q128JVSQ and the communication power controller is restarted; in the BOOTLOADER stage, the upgrade program is transferred to the internal FLASH of the GD32F405RG, and the update program is also run after the verification is passed. The overall design and specific implementation methods of the system are described in detail. The test results show that the system successfully completed the software upgrade of the communication power controller within 15 minutes, and the communication power controller operates normally after the upgrade. This software upgrade method reduces the economic investment in upgrading the maintenance process of the communication power supply, and improves the sustainability and stability of the communication power supply.

In response to the current situation of massive network data volume, increasing attention and demand for network data confidentiality, an SM4 cryptographic coprocessor based on the Hummingbird E203 open-source RISC-V processor has been designed and implemented. Based on the Hummingbird E203 MCU platform, the SM4 cryptographic coprocessor has been extended on the Hummingbird E203 through 5 custom extension instructions. Users can call the coprocessor core to encrypt and decrypt data by writing program code on the software side. Compared with no extension instructions, its throughput can reach 153.75 times. Simultaneously studying the SM4 encryption and decryption algorithm, implementing module multiplexing for key extension and repeated encryption and decryption parts to reduce circuit area. Under the UMC 28nm process, the combined area of the SM4 coprocessor is 7098.8 μm ², with a maximum clock frequency of 200MHz and a data throughput rate of 775.758Mbit/s. The SM4 coprocessor can achieve a data throughput rate of 150.588Mbit/s at a clock frequency of 100MHz.

To address the issues of slow processing speed, low accuracy, and high hardware resource consumption in traditional license plate recognition systems, an efficient license plate recognition system was designed and implemented. This system is based on Field-Programmable Gate Array (FPGA) and Binary Neural Network (BNN) technology. By combining hardware acceleration with algorithm optimization, the system significantly enhances license plate recognition performance. Experimental results show that the system achieves a recognition accuracy of 96.46% and reduces the recognition time to 12 milliseconds. Compared to traditional license plate recognition algorithms and CNN-FPGA solutions, this system demonstrates significant advantages in hardware resource consumption, recognition speed, and accuracy, providing an efficient and resource-friendly solution for license plate recognition.

Aiming at the current problems of short memory life and high cost, we chose to use the domestic microcontroller GD32 to reduce the cost, and adopted the equalization loss algorithm to extend the memory life, and designed a high-capacity data storage system. The system takes GD32 as the control core, two pieces of NAND Flash as the storage medium, connects through the EXMC interface that comes with GD32, uses two RS422 to communicate with the host computer for data, one way to transmit the storage data, one way to carry out the command control, uses the host computer to control the state of the memory, and controls the wear and tear of the NAND Flash block through the balanced loss algorithm. After testing, the system storage capacity reaches 32GByte, the writing speed reaches 1MByte/s, the NAND Flash service life is improved, the performance is stable, and it can meet the needs of long-time use and large-capacity data storage.

Targeting the security concerns regarding the transmission of data from embedded devices in contemporary Internet of Things networks, a novel scheme for MQTT-based trusted device authentication and secure data transmission, leveraging TrustZone technology, has been devised. This scheme involves enhancements to the MQTT communication protocol and the design of prototypes for gateways and data acquisition devices that communicate via this protocol. Device identity authentication, alongside data encryption and tamper-resistance during transmission, are achieved through the implementation of a hybrid domestic commercial cryptography algorithm. The integration of TrustZone technology facilitates the isolation of software and hardware elements within the gateway system, thereby safeguarding the secure storage of critical information such as keys and lists of trusted devices. Both theoretical security analysis and empirical testing affirm that the proposed solution effectively elevates the security of privacy data transmission and storage in IoT embedded contexts, aligning well with real-world application requirements.

A surface-potential-based I-V model for junctionless gate-all-around transistors is presented in this paper. Based on the one-dimensional Poisson equation, combined with the corresponding boundary conditions, the nonlinear system of transcendental equations based on physical principles in two analytical models is sequentially solved using the Runge-Kutta algorithm, and the numerical models of the surface potential, midpoint potential, and gate pressure are established. Subsequently, Pao-Sah integration is used to derive the drain current of gate-all-around field effect transistors by using the results of the surface potential expressed in form of the intermediate parameter. The proposed physics-based I-V model results exhibit good agreements with numerical and experimental data, validating the feasibility of the modeling approach for gate-all-around field effect transistors. Moreover, this method realizes the combination of analytical and numerical models and achieves a good balance between accuracy and efficiency.

Neural Radiance Fields (NeRF) is an emerging method for reconstructing 3D scenes, garnering significant attention for its potential applications in the field of robotics. NeRF utilizes multi-layer perceptrons (MLP) to learn representations of 3D scene features, enabling high-fidelity image rendering while providing a robust foundation for robotic navigation, localization, and perception in complex environments. The core processes of NeRF include ray sampling, feature extraction, and volume rendering, which are characterized by high computational demands and irregular memory access patterns. These challenges limit its deployment on current hardware platforms, particularly on edge devices. To advance the practical application of NeRF technology, new hardware architectures and solutions for co-optimization of hardware and software are necessary. This paper systematically elucidates the principles and evolution of NeRF technology, exploring the performance bottlenecks encountered during its hardware execution. It provides a detailed review of existing NeRF accelerator works, analyzing their commonalities and differences. Furthermore, it discusses the technical limitations and challenges of NeRF accelerators in various application scenarios. Finally, the paper offers recommendations for future developments, aiming to inspire further application and optimization of NeRF technology.

Robots represent a revolutionary engine of new productive forces, reshaping human life and work. Simultaneous Localization and Mapping (SLAM) technology enables robots to navigate autonomously in unknown environments and construct maps of their surroundings, serving as the cornerstone for the intelligence of autonomous mobile robots. However, because SLAM algorithms are complex and computationally intensive, implementations based on general-purpose CPU chips suffer from long delays and high power consumption, which do not meet the real-time and power consumption requirements of autonomous mobile robots, especially small, micro, and nano robots. Consequently, the design of specialized hardware accelerator chips to accelerate computation-intensive SLAM algorithms has received considerable attention from both the academic and industrial communities in recent years. This article starts with the basic concepts and application scenarios of SLAM technology, highlights the necessity of hardware acceleration for SLAM algorithms, reviews the current research status and development trends from the perspectives of algorithms and dedicated chip design, and discusses the technical challenges and solutions in the research of SLAM dedicated chips, providing suggestions for future development.