In order to improve the measurement accuracy and resolution of the phase-sensitive receiver, an all-electronic phase-sensitive receiver based on the all-phase Fast Fourier Transform (apFFT) algorithm was designed. The hardware is a two-take-two Dual-Channel structure, and the process is synchronized by two machines, and the calculation results are output after comparison. The DDS generator was used to build a test platform, the function of the scheme was simulated and verified, and the on-site track circuit combination frame was connected to the field test. The experimental results show that the design can accurately detect the occupancy state of the train in the track section, distinguish the random noise and harmonic signal on the rail. It’s anti-interference ability is excellent, and the phase difference measurement error is less than 0.3°. This scheme is an electronic improvement of the existing microelectronic phase-sensitive track circuit receiver, the circuit is simple, the phase difference calculation is completely completed by software, the reliability is high, and it can be used for the coded or non-coded section of the 25Hz phase-sensitive track circuit using 50Hz alternating current traction.

Real-time is a crucial feature in embedded test platform development, as it enables the platform system to respond quickly to task events. In most cases, there are many tasks running on the platform and different types, so in order to solve the problem of how to prioritize the execution of real-time tasks when there are many tasks and the relationship between tasks is diverse, this paper proposes a multi-DAG real-time priority scheduling algorithm (MDRTPS), which is mainly divided into three steps: (1) real-time task separation for multiple DAGs, The separated real-time task set and the normal task set use different priority algorithms and resource allocation. (2) Maintain three scheduling queues, and the queues coordinate the ordering between different DAG tasks, and (3) the last scheduler schedules tasks to the processor core based on the earliest completion time. Experimental results show that the MDRTPS algorithm is better than the HEFT algorithm and CPOP algorithm in terms of task span and response speed of real-time tasks.

The analog source holds an important position in the test and calibration system of radio radar equipment. The beacon machine equipped with a certain type of Doppler radar has defects such as being bulky and heavy, and being unable to simulate Doppler signals, making it difficult to meet complex test requirements. Therefore, a small dynamic analog source based on the implementation of FPGA was designed. This analog source, through the collaborative operation of FPGA and digital DAC, achieves rapid frequency adjustment, enabling the carrier signal to superimpose Doppler information. In addition, the signal frequency and amplitude generated by the analog source have flexible control methods. It can not only be adjusted wirelessly and in real-time but also output according to pre-stored data, effectively compensating for the deficiencies of the original beacon machine and providing strong support for the test and calibration work of radar equipment.

The travel and daily activities of visually impaired individuals typically rely on walking sticks, guide dogs, or assistance from others. However, with the advancement of urban planning due to economic development, the complexity of urban layout and road design has significantly increased. Consequently, these traditional methods are no longer sufficient to meet the daily needs of blind individuals. Therefore, it is crucial to prioritize attention towards the visually impaired community and enhance their quality of life. This design focuses on machine vision techniques for denoising, filtering, and target calibration in color information and depth images. Subsequently, machine learning training is employed to achieve image-based functions such as color recognition, obstacle detection, and distance measurement. The analysis results are then converted into audio signals which are outputted through voice feedback to provide users with walking suggestions while alerting them about obstacles that cannot be observed in advance. The ultimate goal is to offer obstacle avoidance services for visually impaired individuals by minimizing the impact of unforeseen obstacles during mobility.

To address the issues of high resource utilization and poor customizability associated with using pre-built AXI interface IP cores, a phased, self-designed approach is proposed to add AXI bus support to a designed MIPS processor core. The design is implemented using Verilog HDL for writing RTL code. The overall logic functionality of the processor was verified in the Vivado simulation environment, and the bitstream file was downloaded to the FPGA development board for prototype verification. Resource utilization and timing were obtained. Finally, the processor was synthesized using the Design Compiler (DC) tool, and the overall area and power consumption of the processor were evaluated. The verification results indicate that the self-designed AXI bus consumes less resources and area compared to directly using an AXI interface IP core. This approach ensures that the AXI bus is added without changing the processor core architecture, significantly reducing the difficulty of replacing the original interface in the processor core with the AXI bus interface. It not only reduces integration complexity but also ensures a high degree of customization to meet specific system requirements and performance demands.

In this paper, the failure analysis phenomena of a high-density packaging product for spacecraft under random vibration in astronautical environment are analyzed, and the finite element simulation model is established by applying conditions based on the structural model of the product. The results of simulation and failure analysis show that the device breaking bond wire under vibration loads causes fatigue damage and instantaneous fracture in two steps, causing device failure. Based on the results of this analysis, the bonding wire models with different lengths were established and simulated under the condition of true random vibration of spaceflight.

电子档案数据量通常较大，结构也比较复杂，跨域检索时需要设计高效的数据存储和检索方案，以提高检索准确度。为此，提出了基于云存储的电子档案数据跨域安全检索算法研究。在最优存储节点下，利用云存储节点分别向不同区域的存储节点传输一个电子档案文件，利用分层原理，计算跨域节点之间的距离，通过阈值分级确定云存储节点的数量，分层存储电子档案数据。采用Fourier变换方法，查询重复电子档案数据，在Fourier变换域，重建电子档案数据，给出需要删除的数据，结合逆变换处理，计算出数据的4阶混合累积，完成电子档案重复数据的删除。将聚类中心与所有电子档案数据之间的平均关联度作为电子档案数据的检索空间，确定满意度向量，判断检索空间中电子档案数据的满意度，采用梯度法修正满意度向量，根据用户检索关键词的关联度，实现电子档案数据的跨域安全检索。实验结果表明，文中算法对电子档案数据的自相关检索性能较好，可以将跨域安全检索的查准率提高到90%以上。

Aiming at the problems such as wide distribution and lack of centralized management of distributed photovoltaic power stations, a distributed photovoltaic power station monitoring system based on LoRa and NB-loT is designed. The system collects temperature, humidity, light intensity, voltage, current and other data of distributed photovoltaic power station through wireless terminal nodes, and then carries out networking through LoRa wireless communication technology. After gathering the collected data to the gateway, it relies on NB-IoT wireless technology to upload it to OneNET cloud platform, and the User side retrieves cloud platform data to monitor distributed photovoltaic power plants. The experiment shows that the system has low cost, flexible network and can run stably for a long time, which can meet the demand of power station monitoring.

Sensors often employ metals or semiconductors as their sensitive components.When semiconductor materials are subjected to external optical or thermal stimuli,their electrical conductivity undergoes significant changes,leading to temperature drift in the sensor’s output signals.This temperature drift severely impacts the measurement accuracy and application scope of sensors.To enhance their temperature ability,temperature compensation is essential.Pressure sensors,due to factors such as the piezoresistive coefficient being influenced by temperature,and the temperature sensitivity coefficient is typically negative.The design employs a constant current source with a positive temperature coefficient as the excitation driver for the sensor.The Wheatstone bridge,after being compensated through series and parallel resistance methods,is then utilized to perform sensitivity temperature compensation on the sensor.Experimental results have demonstrated that after undergoing compensation from this two-stage circuit,piezoresistive pressure sensors exhibit stabilized output signals within a range of -50℃ to 75℃,with errors reduced to less than 0.35%FS .This approach effectively mitigates the impact of temperature drift,thereby enhancing the sensor’s overall performance and reliability across a broader temperature spectrum.

The laser line scanning camera projects a linear laser beam onto the surface of the measured object, with its reflected light captured by a camera equipped with a CMOS image sensor based on FPGA. By employing the center point method, the two-dimensional pixel coordinates of the laser line are extracted to reconstruct the complete spatial coordinates of the object. However, due to the influence of equipment and environmental factors, the image often exhibits a non-continuous phenomenon of the laser line. Addressing this issue, this paper proposes a Lagrange interpolation algorithm based on FPGA, which accomplishes the fitting of discontinuous laser line pixel coordinate curves. The algorithm comprises sub-modules for floating-point addition, subtraction, multiplication, division, comparison, and sequential loop control functions. Experimental results demonstrate that this module operates at a significantly higher speed compared to software executed on a host computer, ensuring real-time performance of the system while achieving high-precision fitting, thereby enhancing the overall stability of the system.

Aiming at the shortcomings of the traditional defogging algorithm and meeting the real-time requirements of the defogging system, an improved defogging algorithm is proposed and designed with FPGA. Firstly, a Gaussian low-pass filter is used to retain the low-frequency information of the image; secondly, the rough transmittance map of the foggy image is obtained by combining the a priori theory of the dark channel with the bilateral filtering to obtain the refined transmittance map; and lastly, the foggy image is obtained by the foggy day imaging model. At the same time, the improved algorithm is optimized with FPGA. The experimental results show that the improved defogging algorithm enhances the defogging effect on images with high-brightness areas compared to other defogging algorithms. When performing video image defogging on an FPGA platform, it can achieve a speed of 60 frames per second, meeting real-time requirements.

With the rapid development of VLSIIC manufacturing process and the continuous improvement of integration, the difficulty of chip timing convergence has become increasingly prominent. As one of the core indexes in the physical design of digital chips, timing is of great importance. In integrated circuit design, buffers are added to optimize fan-out and reduce interconnect latency, thereby improving timing performance. However, due to the limitations of EDA tools in predicting the position of standard cells, the method of automatically inserting buffers may be unreasonable. In this study, the placement and route design of an ASIC chip was discussed in depth. Innovus was used as a design tool to optimize the placement stage through a method targeted at buffer insertion. The experimental results showed that this method significantly improved the design result after placement and route, and accelerated the time sequence convergence process.

In the face of the problems of hardware development constraints, software development, hardware resource constraints, and insufficient testing in the application of embedded development boards in the aerospace field, virtualization solutions are introduced for the hardware platform on which a certain type of flight control software depends. Firstly, the AArch64 instruction test set was written to verify the credibility of QEMU dynamic translation, and Flash was successfully mounted by debugging, tracing, changing, and compiling the QEMU source code. Secondly, a new equipment simulator was created, the network communication mode of the model machine was adjusted, and the virtual machine, simulator and model machine were jointly debugged to ensure the normal data transmission, so as to smoothly build a virtual platform. Furthermore, an integrated development environment is designed to support the visual construction of the virtual platform, remote debugging of source code, target code coverage statistics and other functions to improve the convenience and reliability of the virtual platform. Finally, it is observed that the simulation results of a certain type of flight control software are consistent between the real platform and the virtual platform, which verifies that the virtual platform is real and usable.

When conducting dynamic tests on a structural model using wind tunnel experiments, it is necessary to store, record, and analyze the status information of multiple test processes using a data recorder. The data recorder utilizes an LVDS (Low Voltage Differential Signaling) interface. To facilitate the issuance of commands and playback tests with an upper computer during the ground phase, an LVDS to Ethernet test fixture was designed.This device uses an FPGA (Field-Programmable Gate Array) as the main control chip. It employs 8b/10b encoding and decoding to ensure the stability of signal transmission over the LVDS line. Communication with the upper computer is achieved through an Ethernet interface. Data from the recorder is transmitted via LVDS to the FPGA’s RAM. Dual RAM buffering is used to enhance transmission efficiency. Subsequently, the data in the RAM is encapsulated into Ethernet UDP/IP frame format. On top of the UDP protocol, a command-data "handshake" operation is achieved through alternating dual RAM buffers. CRC (Cyclic Redundancy Check) and data retransmission methods are used to reduce the error rate during transmission. Finally, the data is sent to the upper computer through a physical layer chip.Validation has shown that data transmission using LVDS, FPGA, and Ethernet is feasible, with good stability and reliability, making it suitable for practical engineering applications.

For the conventional radar target clutter detection technology, the background power level estimation of each azimuth-distance unit is obtained by the recursive update of the continuous scanning period samples in the resolving unit, but this estimation method fails when there are a large number of interfering target samples in the continuous scanning period samples of the resolving unit. In this paper, this paper draws on the sample screening technology in the spatial constant false alarm to the time domain constant false alarm, and proposes an OTSU-CCA-based clutter detector to improve the accuracy of background power level estimation by eliminating the possible interference target samples in the continuous scanning period samples, and then improve the detection performance of clutter map.

The high-performance DSP + FPGA architecture can meet the real-time processing requirements of the embedded image processing system for large amounts of data and complex algorithms. The traditional DSP + FPGA architecture uses the parallel External Memory Interface as the data transfer interface, with a large number of traces, difficult PCB wiring, and many failure points. The use of high-speed serial buses can solve the above problems. This paper proposes an image processing system based on high-speed serial buses and DSP+FPGA architecture. PCIe bus is used as the image data channel between DSP and FPGA, SRIO bus is used as the link between DSP and DSP, and SGMII bus is used as the data channel between DSP and PHY chip. High-speed serial buses make the data transfer rate higher, easier layout of the PCB, lower electromagnetic interference, and better noise immunity. The system designed in this paper has been deployed and operated stably in practical locations, which demonstrates that the design is feasible and the system is reliable.

In this paper, a novel class-F voltage doubler rectifier is proposed for radio frequency energy harvesting (RFEH). In the proposed structure, two different harmonic termination networks are employed to block the harmonics of voltage doubler diodes and reshape current waveform and voltage waveform. Thus, the power conversion efficiency (PCE) of the conventional voltage doubler rectifier can be improved significantly. For validation, a prototype is fabricated and measured. The measured peak PCE is 76.5% with a 13 dBm input power and a 1600 Ω load. Besides, the input power range for PCE high than 50% is from 1.8 to 15.5 dBm.

A high-precision positioning watch based on intrinsic safety was designed and implemented to address the issues of portable positioning tags placed at the waist in coal mines, which are difficult to seek help in emergency situations, lack of LCD display of escape route information, and difficulty in perceiving vibrations. The battery output of the watch adopts a three-level protection to achieve a higher safety level. The heart rate monitoring sensor is used to collect the heart rate status of workers entering the well in real-time, monitor their physical health status. UWB positioning technology and tunnel base station are used for real-time distance measurement, and the positioning accuracy is improved from meter level to centimeter level. Through UWB communication network, the watch can achieve two-way communication with the ground dispatch room. In emergency situations, one click underground rescue is required, and when gas exceeds the limit, evacuation information is received from the ground. The LCD displays the escape route information. At the same time, the watch has multifunctional alarm prompts such as sound, light, and vibration, providing more powerful protection for safe underground operations of miners.