This study focuses on the power integrity optimization analysis of a domestic power supply validation board designed for a 48V input, 0.8V output at 1000A current demand, targeting the challenges of low-voltage, high-power requirements. A simulation-based design strategy for the power distribution network (PDN) is proposed to enhance the performance of the power system. The study begins with a simulation analysis of the PCB layout, power planes, and via current carrying capacity, optimizing the component layout and via design to significantly reduce voltage drop by 14.5mV, decrease the power plane circuit density by 61%, lower the power system loss by 17.2W, and slow down the via current to half its original value. Additionally, the thermal effect of using heat sinks is simulated, showing a temperature reduction of up to 27.81°C with the application of heat sinks. Through power plane resonance simulation analysis, the power plane resonance noise is effectively controlled within 0.001% of the output voltage. Fabrication and practical testing confirm that the optimized PCB ripple noise is within 1% of the rated output voltage, with an overall efficiency exceeding 90%, demonstrating that the power system based on domestic components has achieved a leading industry level. The results indicate that the proposed simulation-based design strategy effectively mitigates power integrity risks such as voltage drop, overcurrent, and overheating, improves PCB design efficiency, and enhances the reliability and stability of the power system.

In this paper, an 8-bit current-steering DAC based on MO-TFT technology is implemented, which includes a timing refresh module, a synchronous register circuit, a segmented decoder circuit, a switch driver circuit, a switch array and a current source array. The timing refresh structure is designed in the digital circuit to solve the traditional bootstrap logic gate charge leakage caused by the current source switch driving voltage drop, to avoid the problem of sampling errors in low frequency signals. The structure of differential dual decoding is proposed so that the open and close signals can arrive at the switch driver circuit at the same time, which ensures the symmetry of the voltage rise and fall windows in the driver circuit and reduces the output glitter. At the same time, the D flip-flop in the digital circuit and the logic gate in the decoder circuit are used to realize the driver enhancement circuit, which ensures that the high bit unit current source in the analog circuit can be driven and the conversion rate is improved. Finally, an 8b current DAC with power consumption of 5.8mW, output current swing of 301.46µA, and maximum conversion rate of 32KS/s is implemented. Under the condition that the standard deviation of random matching error per unit current source is 0.1, the SFDR at Nyquist frequency can reach 42.43dB, and the area is 73mm2.

Millimeter-wave radar, as an important sensing technology, is widely used in applications such as autonomous driving, intelligent transportation, security monitoring, and industrial inspection. It offers high precision and strong anti-interference capability.With the continual advancement in the research of power integrity, signal integrity, and thermal stability, significant progress has been achieved both domestically and internationally in these domains. However, existing studies predominantly focus on individual aspects, lacking a comprehensive consideration of the interactions between power noise, signal interference, and thermal effects. This study introduces a unified simulation approach that integrates power, signal, and thermal effects through multi-physics analysis to optimize the overall performance of millimeter-wave radar hardware systems. Additionally, a capacitor optimization strategy is proposed, which involves increasing capacitor configurations within critical frequency bands to effectively enhance power integrity and ensure system stability. Simulation and experimental results demonstrate that the proposed method significantly improves the impedance characteristics of the Power Distribution Network (PDN), reduces power noise and signal interference, and optimizes the system's thermal management. Through these innovative approaches, this research enhances the comprehensive performance of high-speed circuit systems from multiple dimensions, providing new optimization strategies and methodologies for the design of high-performance hardware tailored for millimeter-wave radar applications.

In the process of special equipment testing, the need for test data collection and storage, for the test process, the data transmission rate is not high and the problem of transmission reliability. In this paper, we design a data transmission system combining FPGA and Gigabit Ethernet, using UDP protocol to increase the data transmission rate while adding data retransmission mechanism and packet counting to improve the reliability of data transmission. The experiment is verified on XILINX's FPGA board, and the experimental results prove that FPGA+Gigabit Ethernet data transmission is feasible and effectively improves the data transmission rate, has good maintainability and stability, and can be applied in practical engineering.

This paper reviews the design and optimization of bioimpedance detection chips, focusing on the applicable scenarios of dual-electrode and quad-electrode and their trade-offs in measurement accuracy and portability. According to different detection requirements, the implementation principles and characteristics of ADC method, DAC method, successive approximation method, half-sine DAC method and baseline elimination technology are discussed in detail. Studies have shown that dual-electrode combined with efficient DAC method has significant advantages in portable devices, while the four-electrode configuration is suitable for high-precision impedance measurement scenarios. This paper provides theoretical support for the design of bioimpedance detection chips and looks forward to its application prospects in wearable medical devices and dynamic monitoring.

With the advancement of research on single-cell heterogeneity, cellular electrophysical properties have become a crucial focus in disease diagnosis and precision medicine. Microfluidic bioelectrical impedance detection chips measure the impedance changes of cells in an electric field with high precision, enabling the label-free acquisition of cellular electrophysical characteristics such as cell size, membrane capacitance, and cytoplasmic conductivity. This significantly enhances the ability to detect cellular heterogeneity. Compared to traditional methods, microfluidic bioelectrical impedance detection chip technology offers advantages such as high sensitivity, simplicity of operation, and non-destructive detection, demonstrating broad application prospects in early disease diagnosis, drug screening, and personalized treatment. This review first elaborates on the basic principles and system design of the technology, then analyzes the progress in optimizing microfluidic channels and electrode configurations, and discusses its applications in cell classification, drug evaluation, and other fields. Finally, the review examines current technical challenges and future development trends, highlighting its potential for widespread application in precision medicine and early disease diagnosis.

Brain organoids are three-dimensional cell aggregates produced in vitro through the self-organization and differentiation of human pluripotent stem cells, which can partially recapiculate the structure and function of the brain in humans. Microelectrode array (MEA) technology is capable of high-throughput detecting the electrophysiological activities of brain organoids with low damage , and high spatiotemporal resolution, thereby providing an efficient platform for the functional characterization of brain organoid neural networks. The integration of brain organoids with MEA technology has attracted widespread attentions in the fields of nervous system development and disease mechanism research, biological neural network intelligent computing, and in vivo repair. In the area of nervous system development and disease mechanism research, MEA technology can long-term track the dynamic developmental process of brain organoids in real time and probe the pathogenesis of diseases by detecting the electrophysiological activities of brain organoids derived from various nervous system diseases . In the avenue of biological neural network intelligent computing research, brain organoids are excellent computing devices attributed totheir heterogeneous three-dimensional network structures and plasticity. Therefore, a highly efficient computing platform with low energy cost can be constructed through interaction of brain organoids with MEA. Furthermore, MEA technology shows potential technical application prospects in nervous system repair based on brain organoids. Keywords: Brain Organoids，Microelectrode Arrays, Neurological Disease, Neural Computing, Neural Repair

Electrical stimulation technology has been widely applied in various biomedical fields, including cardiac pacemakers, cochlear implants, muscle reconstruction, vision restoration, and epilepsy suppression. Compared to traditional drug therapies or surgical methods, electrical stimulation offers advantages such as reduced invasiveness, greater flexibility, improved recoverability, and the elimination of risks associated with drug dependency and addiction. Due to the advantages of integrated circuits, including low power consumption, high reliability, strong programmability, ease of multifunctional integration, and suitability for mass produc-tion, they have recently become the primary choice for designing electrical stimulators, meeting the demands for miniaturized, intelligent, and cost-effective biomedical applications. However, the integration of high-density electrodes with stimula-tion-generating circuits presents significant challenges in designing electrode-tissue interfaces. This paper begins with the elec-trode-tissue interface and provides a comprehensive overview of integrated circuit design for implantable electrical stimulators, including fundamental driver circuit topologies and high-performance complex designs. It emphasizes the analysis of the reliability and safety of biomedical implantable chips and introduces innovative designs that integrate stimulators with energy harvesting modules in closed-loop systems. This review also discusses the future directions of electrical stimulation technology and interface systems including our research group's work on electrical stimulation and interface circuits.

The electronic controller of an aero-engine is a complex circuit system designed with numerous large-scale integrated circuits as the core. The traditional contact-based fault injection and detection methods relying on physical probes can no longer meet the testability design requirements of such complex circuits. This paper proposes a fault injection and detection method based on boundary scan for the core circuit of the aero-engine electronic controller. Based on the analysis of the core circuit, a boundary scan daisy chain and a boundary scan controller are designed, which have the ability to conduct fault injection and detection based on the interconnection between chips and the boundary scan units inside the chips. Combined with the overspeed protection logic of the engine, the fault injection and detection functions of the two methods are verified.

Bioimpedance measurement technology serves as a vital tool for medical diagnosis and health monitoring in various emerging medical instruments, in which the high-precision readout circuit is a crucial module for achieving accurate diagnoses. Traditional readout circuits in bioimpedance measurement systems often utilize SAR ADCs, which can hardly achieve an accuracy exceeding 12 bits to meet the increasingly high-precision demands for bioimpedance readout without calibration. To deal with this issue, this paper presents a 24-bit incremental Σ-Δ ADC designed for bioimpedance measurement which adopts a 3rd-order, 4-bit, single-loop feedforward structure to reduce quantization noise while accelerate the conversion speed. The design incorporates data weighted averaging (DWA) technique to mitigate the nonlinearity caused by multibit feedback DAC’s mismatch, significantly enhancing the ADC’s accuracy. In addition, system-level chopping is employed to eliminate systematic offset in the ADC frontend. A configurable digital filter is designed to achieve flexible tradeoff between measurement time and by configuring different oversampling ratios (OSR). The ADC is fabricated using a 180 nm process, with measurement results under an OSR of 128 showing that the ADC achieves an ENOB of 17.80, a SNR of 108.89 dB, a THD of -113.29 dB, an equivalent input RMS noise of 2.95 μVrms. The power consumption is 930 μW for the whole ADC chip.

The traditional RF power supply of the mass spectrometer is driven by crystal, and it’s frequency is fixed and nonadjustable, which makes the debugging of the RF power supply inconvenient in the development stage. A signal source system for RF power supply by using direct digital frequency synthesis (DDS) and embedded technology was designed in order to resolve the shortage .The system was composed of DDS chip and STM32 series microcontroller based on ARM., It can output sine wave signal in single and sweep mode by the control of upper computer. The scanning range of this system is 100kHz~1Mhz.The precision is better than 0.02% under 1Mhz..It can be used as a signal source for multiple RF power supply. The experiment shows that the Ion trap RF power can output peak-to-peak voltage up to 3.5kV and resonant frequency 1.0136MHz by the drive of the system.

At present, a single positioning technology cannot achieve good positioning results both indoors and outdoors. For example, Beidou positioning technology can achieve high accuracy in outdoor positioning, but its performance in indoor positioning is poor. Bluetooth has high positioning accuracy in indoor positioning, but it falls short in outdoor positioning. Based on the above situation, this article proposes an indoor and outdoor collaborative positioning technology based on Beidou and Bluetooth positioning. The Beidou and Bluetooth positioning systems are unified in the same coordinate system, and an improved BP neural network is used to achieve seamless switching in all scenarios. At the same time, a positioning fusion strategy is introduced for indoor and outdoor buffer areas to improve positioning accuracy. The experimental results show that in all scenarios, the average positioning error of the collaborative positioning system has increased by 0.7%, 31.7%, and 2.4% compared to a single positioning system, respectively, proving the effectiveness and accuracy of the method.

Unlike artificial neural networks (ANNs), spiking neural networks (SNNs), representing the third generation of neural network technology, perform computations based on the mechanisms of biological neurons. They use sequences of spike signals to transmit information, demonstrating significant advantages in energy consumption and high-speed processing of large-scale data. Currently, converting high-precision ANNs to SNNs is considered one of the most promising methods for generating SNNs. However, mainstream ANN-to-SNN conversion methods have their limitations: firstly, they do not support negative spikes, making it difficult to express negative spikes collected by dynamic vision sensor (DVS) cameras; secondly, it is challenging to achieve both low latency and high precision during the conversion process. To address these issues, this paper proposes a novel spiking neuron capable of globally representing both positive and negative spikes. Additionally, a stepwise Leaky ReLU activation function and a regional convergence testing algorithm are proposed to achieve zero-error conversion from ANN to SNN. With these methods, we achieve globally expressive, high-precision, low-latency, and highly robust ANN-to-SNN conversion. Our approach demonstrates outstanding performance on the CIFAR10 and CIFAR100 datasets.

In order to solve the problem that the output voltage of the charge pump is not adjustable, a charge pump circuit with controllable output voltage is designed, which is composed of a high-frequency oscillation circuit, a negative voltage generating circuit, a reference circuit and a feedback module. Compared with the traditional charge pump, the output voltage is more flexible, the output voltage ripple is smaller, and the overall circuit is based on the eastern 0.18 μm CMOS process. The simulation results show that the output voltage ripple is within 3mV at room temperature at an input current of 100μA. In the range of -40°C~125°C, the process angle output ripple is within 5mV. The charge pump circuit works stably at the output voltage of -3V~0V, and has been applied to the rail-to-rail op amp project.

T型栅PMOS器件因其强抗辐照能力，低寄生电容，逐渐成为RFSOI电路中必不可少的器件。而跨导是MOS器件中的一个关键参数，但T型栅PMOS器件的跨导会在栅极电压增大时，出现双峰效应，影响电路研制的判断。本文首先结合实测数据和3D TCAD仿真结果，深入剖析了T型栅PMOS器件跨导双峰效应的内部机理。并从温度、主栅尺寸和次栅尺寸三个方面分析阐述了其对双峰效应的影响。最终，基于T型栅PMOS器件版图结构，提出了一种可抑制双峰效应的改进结果，通过了仿真和流片验证，可以良好地适用于SOI工艺T型栅PMOS结构电路设计当中。

Before the mass production of chip engineering, it is necessary to conduct a comprehensive circuit performance test on the chip, screen the chips that meet the requirements, and avoid unqualified chips from entering the market. PMIC (Power Management IC) is a power management chip that realizes a variety of functions such as power conversion, power conversion, and current control through built-in DC-DC converters, current control, and protection mechanisms. Therefore, it is necessary to consider whether the technical indicators of the chip meet the requirements of use. In this paper, taking the UC3842 chip as an example, an analog chip performance test scheme based on Huafon STS8200 is proposed. In this paper, the test methods and test procedures of several important parameters of the chip (reference voltage, load regulation, linear regulation, oscillator frequency, rising and falling edge time, etc.) are studied. Finally, the experimental results of each parameter are within the range of effective values, and the results show that after testing 10 chips and LOOP100 the 10th chip, the test yield of the chip is 100%. It shows that the test scheme is real and effective.

To improve the SNR of frequency-hopping signal, a novel algorithm based on intrinsic time-scale decomposition is proposed. Firstly, the sampling signal is decomposed by ITD method to get rotational components and trend component. Then, the principle for noise judging is built by combing the ITD and the abrupt change of the cross-correlation peak between the rotational component and the original signal. Next, judging and deleting the noise components according to the principle. Finally, the signal is reconstructed with the rest of rotational components. Simulation results show that the algorithm is effective. To ensure that the distortion of the reconstructed signal is less than 5%, the algorithm can be adapted to -1 dB. The SNR of reconstructed signal is improved above 9 dB at least when the SNR of original signal is greater than -1 dB.

Real-time is a crucial feature in embedded test platform development, as it enables the platform system to respond quickly to task events. In most cases, there are many tasks running on the platform and different types, so in order to solve the problem of how to prioritize the execution of real-time tasks when there are many tasks and the relationship between tasks is diverse, this paper proposes a multi-DAG real-time priority scheduling algorithm (MDRTPS), which is mainly divided into three steps: (1) real-time task separation for multiple DAGs, The separated real-time task set and the normal task set use different priority algorithms and resource allocation. (2) Maintain three scheduling queues, and the queues coordinate the ordering between different DAG tasks, and (3) the last scheduler schedules tasks to the processor core based on the earliest completion time. Experimental results show that the MDRTPS algorithm is better than the HEFT algorithm and CPOP algorithm in terms of task span and response speed of real-time tasks.

The analog source holds an important position in the test and calibration system of radio radar equipment. The beacon machine equipped with a certain type of Doppler radar has defects such as being bulky and heavy, and being unable to simulate Doppler signals, making it difficult to meet complex test requirements. Therefore, a small dynamic analog source based on the implementation of FPGA was designed. This analog source, through the collaborative operation of FPGA and digital DAC, achieves rapid frequency adjustment, enabling the carrier signal to superimpose Doppler information. In addition, the signal frequency and amplitude generated by the analog source have flexible control methods. It can not only be adjusted wirelessly and in real-time but also output according to pre-stored data, effectively compensating for the deficiencies of the original beacon machine and providing strong support for the test and calibration work of radar equipment.