Aiming at the problems of scarce hardware resources and low development and testing efficiency in airborne communication software development, a real-time simulation verification platform based on Qemu and Huawei's private cloud is designed and implemented. It simulates and runs a configurable embedded target machine environment and Rehua operating system, realizes TDMA protocol time slot simulation, and improves simulation real-time performance through the SCHED_RR priority strategy. It uses network namespaces and VPN technology to build a multi-node virtual network. This platform is used for real-time simulation and automated testing of embedded protocol software for airborne communication equipment, effectively improving the efficiency and quality of software development and testing.

Millimeter-wave radar, as an important sensing technology, is widely used in applications such as autonomous driving, intelligent transportation, security monitoring, and industrial inspection. It offers high precision and strong anti-interference capability.With the continual advancement in the research of power integrity, signal integrity, and thermal stability, significant progress has been achieved both domestically and internationally in these domains. However, existing studies predominantly focus on individual aspects, lacking a comprehensive consideration of the interactions between power noise, signal interference, and thermal effects. This study introduces a unified simulation approach that integrates power, signal, and thermal effects through multi-physics analysis to optimize the overall performance of millimeter-wave radar hardware systems. Additionally, a capacitor optimization strategy is proposed, which involves increasing capacitor configurations within critical frequency bands to effectively enhance power integrity and ensure system stability. Simulation and experimental results demonstrate that the proposed method significantly improves the impedance characteristics of the Power Distribution Network (PDN), reduces power noise and signal interference, and optimizes the system's thermal management. Through these innovative approaches, this research enhances the comprehensive performance of high-speed circuit systems from multiple dimensions, providing new optimization strategies and methodologies for the design of high-performance hardware tailored for millimeter-wave radar applications.

This study focuses on the power integrity optimization analysis of a domestic power supply validation board designed for a 48V input, 0.8V output at 1000A current demand, targeting the challenges of low-voltage, high-power requirements. A simulation-based design strategy for the power distribution network (PDN) is proposed to enhance the performance of the power system. The study begins with a simulation analysis of the PCB layout, power planes, and via current carrying capacity, optimizing the component layout and via design to significantly reduce voltage drop by 14.5mV, decrease the power plane circuit density by 61%, lower the power system loss by 17.2W, and slow down the via current to half its original value. Additionally, the thermal effect of using heat sinks is simulated, showing a temperature reduction of up to 27.81°C with the application of heat sinks. Through power plane resonance simulation analysis, the power plane resonance noise is effectively controlled within 0.001% of the output voltage. Fabrication and practical testing confirm that the optimized PCB ripple noise is within 1% of the rated output voltage, with an overall efficiency exceeding 90%, demonstrating that the power system based on domestic components has achieved a leading industry level. The results indicate that the proposed simulation-based design strategy effectively mitigates power integrity risks such as voltage drop, overcurrent, and overheating, improves PCB design efficiency, and enhances the reliability and stability of the power system.

In the process of special equipment testing, the need for test data collection and storage, for the test process, the data transmission rate is not high and the problem of transmission reliability. In this paper, we design a data transmission system combining FPGA and Gigabit Ethernet, using UDP protocol to increase the data transmission rate while adding data retransmission mechanism and packet counting to improve the reliability of data transmission. The experiment is verified on XILINX's FPGA board, and the experimental results prove that FPGA+Gigabit Ethernet data transmission is feasible and effectively improves the data transmission rate, has good maintainability and stability, and can be applied in practical engineering.

The electronic controller of an aero-engine is a complex circuit system designed with numerous large-scale integrated circuits as the core. The traditional contact-based fault injection and detection methods relying on physical probes can no longer meet the testability design requirements of such complex circuits. This paper proposes a fault injection and detection method based on boundary scan for the core circuit of the aero-engine electronic controller. Based on the analysis of the core circuit, a boundary scan daisy chain and a boundary scan controller are designed, which have the ability to conduct fault injection and detection based on the interconnection between chips and the boundary scan units inside the chips. Combined with the overspeed protection logic of the engine, the fault injection and detection functions of the two methods are verified.

The traditional RF power supply of the mass spectrometer is driven by crystal, and it’s frequency is fixed and nonadjustable, which makes the debugging of the RF power supply inconvenient in the development stage. A signal source system for RF power supply by using direct digital frequency synthesis (DDS) and embedded technology was designed in order to resolve the shortage .The system was composed of DDS chip and STM32 series microcontroller based on ARM., It can output sine wave signal in single and sweep mode by the control of upper computer. The scanning range of this system is 100kHz~1Mhz.The precision is better than 0.02% under 1Mhz..It can be used as a signal source for multiple RF power supply. The experiment shows that the Ion trap RF power can output peak-to-peak voltage up to 3.5kV and resonant frequency 1.0136MHz by the drive of the system.

At present, a single positioning technology cannot achieve good positioning results both indoors and outdoors. For example, Beidou positioning technology can achieve high accuracy in outdoor positioning, but its performance in indoor positioning is poor. Bluetooth has high positioning accuracy in indoor positioning, but it falls short in outdoor positioning. Based on the above situation, this article proposes an indoor and outdoor collaborative positioning technology based on Beidou and Bluetooth positioning. The Beidou and Bluetooth positioning systems are unified in the same coordinate system, and an improved BP neural network is used to achieve seamless switching in all scenarios. At the same time, a positioning fusion strategy is introduced for indoor and outdoor buffer areas to improve positioning accuracy. The experimental results show that in all scenarios, the average positioning error of the collaborative positioning system has increased by 0.7%, 31.7%, and 2.4% compared to a single positioning system, respectively, proving the effectiveness and accuracy of the method.

Unlike artificial neural networks (ANNs), spiking neural networks (SNNs), representing the third generation of neural network technology, perform computations based on the mechanisms of biological neurons. They use sequences of spike signals to transmit information, demonstrating significant advantages in energy consumption and high-speed processing of large-scale data. Currently, converting high-precision ANNs to SNNs is considered one of the most promising methods for generating SNNs. However, mainstream ANN-to-SNN conversion methods have their limitations: firstly, they do not support negative spikes, making it difficult to express negative spikes collected by dynamic vision sensor (DVS) cameras; secondly, it is challenging to achieve both low latency and high precision during the conversion process. To address these issues, this paper proposes a novel spiking neuron capable of globally representing both positive and negative spikes. Additionally, a stepwise Leaky ReLU activation function and a regional convergence testing algorithm are proposed to achieve zero-error conversion from ANN to SNN. With these methods, we achieve globally expressive, high-precision, low-latency, and highly robust ANN-to-SNN conversion. Our approach demonstrates outstanding performance on the CIFAR10 and CIFAR100 datasets.

T型栅PMOS器件因其强抗辐照能力，低寄生电容，逐渐成为RFSOI电路中必不可少的器件。而跨导是MOS器件中的一个关键参数，但T型栅PMOS器件的跨导会在栅极电压增大时，出现双峰效应，影响电路研制的判断。本文首先结合实测数据和3D TCAD仿真结果，深入剖析了T型栅PMOS器件跨导双峰效应的内部机理。并从温度、主栅尺寸和次栅尺寸三个方面分析阐述了其对双峰效应的影响。最终，基于T型栅PMOS器件版图结构，提出了一种可抑制双峰效应的改进结果，通过了仿真和流片验证，可以良好地适用于SOI工艺T型栅PMOS结构电路设计当中。

Before the mass production of chip engineering, it is necessary to conduct a comprehensive circuit performance test on the chip, screen the chips that meet the requirements, and avoid unqualified chips from entering the market. PMIC (Power Management IC) is a power management chip that realizes a variety of functions such as power conversion, power conversion, and current control through built-in DC-DC converters, current control, and protection mechanisms. Therefore, it is necessary to consider whether the technical indicators of the chip meet the requirements of use. In this paper, taking the UC3842 chip as an example, an analog chip performance test scheme based on Huafon STS8200 is proposed. In this paper, the test methods and test procedures of several important parameters of the chip (reference voltage, load regulation, linear regulation, oscillator frequency, rising and falling edge time, etc.) are studied. Finally, the experimental results of each parameter are within the range of effective values, and the results show that after testing 10 chips and LOOP100 the 10th chip, the test yield of the chip is 100%. It shows that the test scheme is real and effective.

To improve the SNR of frequency-hopping signal, a novel algorithm based on intrinsic time-scale decomposition is proposed. Firstly, the sampling signal is decomposed by ITD method to get rotational components and trend component. Then, the principle for noise judging is built by combing the ITD and the abrupt change of the cross-correlation peak between the rotational component and the original signal. Next, judging and deleting the noise components according to the principle. Finally, the signal is reconstructed with the rest of rotational components. Simulation results show that the algorithm is effective. To ensure that the distortion of the reconstructed signal is less than 5%, the algorithm can be adapted to -1 dB. The SNR of reconstructed signal is improved above 9 dB at least when the SNR of original signal is greater than -1 dB.

Real-time is a crucial feature in embedded test platform development, as it enables the platform system to respond quickly to task events. In most cases, there are many tasks running on the platform and different types, so in order to solve the problem of how to prioritize the execution of real-time tasks when there are many tasks and the relationship between tasks is diverse, this paper proposes a multi-DAG real-time priority scheduling algorithm (MDRTPS), which is mainly divided into three steps: (1) real-time task separation for multiple DAGs, The separated real-time task set and the normal task set use different priority algorithms and resource allocation. (2) Maintain three scheduling queues, and the queues coordinate the ordering between different DAG tasks, and (3) the last scheduler schedules tasks to the processor core based on the earliest completion time. Experimental results show that the MDRTPS algorithm is better than the HEFT algorithm and CPOP algorithm in terms of task span and response speed of real-time tasks.

The analog source holds an important position in the test and calibration system of radio radar equipment. The beacon machine equipped with a certain type of Doppler radar has defects such as being bulky and heavy, and being unable to simulate Doppler signals, making it difficult to meet complex test requirements. Therefore, a small dynamic analog source based on the implementation of FPGA was designed. This analog source, through the collaborative operation of FPGA and digital DAC, achieves rapid frequency adjustment, enabling the carrier signal to superimpose Doppler information. In addition, the signal frequency and amplitude generated by the analog source have flexible control methods. It can not only be adjusted wirelessly and in real-time but also output according to pre-stored data, effectively compensating for the deficiencies of the original beacon machine and providing strong support for the test and calibration work of radar equipment.

The travel and daily activities of visually impaired individuals typically rely on walking sticks, guide dogs, or assistance from others. However, with the advancement of urban planning due to economic development, the complexity of urban layout and road design has significantly increased. Consequently, these traditional methods are no longer sufficient to meet the daily needs of blind individuals. Therefore, it is crucial to prioritize attention towards the visually impaired community and enhance their quality of life. This design focuses on machine vision techniques for denoising, filtering, and target calibration in color information and depth images. Subsequently, machine learning training is employed to achieve image-based functions such as color recognition, obstacle detection, and distance measurement. The analysis results are then converted into audio signals which are outputted through voice feedback to provide users with walking suggestions while alerting them about obstacles that cannot be observed in advance. The ultimate goal is to offer obstacle avoidance services for visually impaired individuals by minimizing the impact of unforeseen obstacles during mobility.

To address the issues of high resource utilization and poor customizability associated with using pre-built AXI interface IP cores, a phased, self-designed approach is proposed to add AXI bus support to a designed MIPS processor core. The design is implemented using Verilog HDL for writing RTL code. The overall logic functionality of the processor was verified in the Vivado simulation environment, and the bitstream file was downloaded to the FPGA development board for prototype verification. Resource utilization and timing were obtained. Finally, the processor was synthesized using the Design Compiler (DC) tool, and the overall area and power consumption of the processor were evaluated. The verification results indicate that the self-designed AXI bus consumes less resources and area compared to directly using an AXI interface IP core. This approach ensures that the AXI bus is added without changing the processor core architecture, significantly reducing the difficulty of replacing the original interface in the processor core with the AXI bus interface. It not only reduces integration complexity but also ensures a high degree of customization to meet specific system requirements and performance demands.

电子档案数据量通常较大，结构也比较复杂，跨域检索时需要设计高效的数据存储和检索方案，以提高检索准确度。为此，提出了基于云存储的电子档案数据跨域安全检索算法研究。在最优存储节点下，利用云存储节点分别向不同区域的存储节点传输一个电子档案文件，利用分层原理，计算跨域节点之间的距离，通过阈值分级确定云存储节点的数量，分层存储电子档案数据。采用Fourier变换方法，查询重复电子档案数据，在Fourier变换域，重建电子档案数据，给出需要删除的数据，结合逆变换处理，计算出数据的4阶混合累积，完成电子档案重复数据的删除。将聚类中心与所有电子档案数据之间的平均关联度作为电子档案数据的检索空间，确定满意度向量，判断检索空间中电子档案数据的满意度，采用梯度法修正满意度向量，根据用户检索关键词的关联度，实现电子档案数据的跨域安全检索。实验结果表明，文中算法对电子档案数据的自相关检索性能较好，可以将跨域安全检索的查准率提高到90%以上。