Integrated Circuits and Embedded Systems

Research and design of all-electronic phase-sensitive receiver based on dual-channel

DIAO Yanmei, CHEN Meiling, YI Liang

Integrated Circuits and Embedded Systems, 2025, 25(1): 67-73. DOI: 10.20193/j.ices2097-4191.2024.0055

区段序号	轨道电压/V	局部电压/V	测试仪结果 /(°)	计算机计算结果/(°)	apFFT 计算结果/(°)	测试结果
1	16.0	110	90.3	89.5	89.5	空闲
2	16.7	110	89.8	90.5	90.5	空闲
3	15.8	110	92.4	91.8	91.8	空闲
4	15.6	110	86.8	87.3	87.4	空闲
5	16.5	110	93.4	93.0	93.1	空闲
6	6.8	110	—	—	—	占用

Table 2 On-site track section test data

Other figure/table from this article

Fig. 1 Schematic diagram of the working principle of a traditional phase-sensitive receiver
Fig. 2 Schematic diagram of the working principle of an all-electronic phase-sensitive receiver
Fig. 3 25 Hz phase-sensitive receiver hardware block diagram
Fig. 4 Safety drive circuit diagram
Fig. 5 Equivalent block diagram of all phase data processing
Fig. 6 Flow chart of dual-machine synchronization mechanism
Fig. 7 DDS signal generator hardware schematics
Fig. 8 Simulation test of DDS test platform
Table 1 Simulation test results
Fig. 9 RMSE of phase difference at different SNR
Fig. 10 On-site testing process