This article proposes an improved plan for the SM3 algorithm using the agile development language BSV.By analyzing the algorithm's operating logic, the algorithm is innovatively split into multiple high-abstraction BSV modules, thereby effectively reducing the design complexity and making it comparable to traditional Verilog design. The code amount is reduced by 60% compared to the previous model. The iterative compression module has a greater impact on the algorithm performance, thus methods such as parallel pipeline and single-round logic optimization are employed for improvement from two aspects, and simulation verification is conducted on the Xilinx ARTIX-7 series FPGA platform with successful serial port debugging. The final results show that only 1 563 LUT resources are consumed to achieve a throughput of 3.2 Gbit/s, which represents up to a threefold improvement in throughput per unit logic resource compared to existing solutions. The maximum operating frequency reaches 375 MHz, with a higher practical value.