Transient circuit simulations often necessitate the construction of linear system models,where the sequential solution of triangular matrices with multiple right-hand terms becomes a time-intensive process.To expedite the computational efficiency of back-substitution for these matrices in transient circuit simulations,this paper proposes a parallel computing method based on a heterogeneous platform.The method prioritizes the computation of multiplications relevant to the solution vector,exploiting the inherent parallelism of back-substitution calculations.The architecture features a core operation array with multiple floating-point calculation units and a control module employing a two-tiered master-slave state machine.Using the Zynq UltraScale series FPGA,specifically the XCZU15EG model,our architecture is compared to an Intel 24-core CPU platform utilizing the MKL solving library in linear matrix resolution experiments.The matrices used exhibit characteristics of being symmetric positive definite,diagonally dominant,and dense with a sparsity exceeding 50%.The proposed acceleration architecture achieves an average speedup factor of 22,with solution errors falling within the range of 10^-17 to 10^-14.The experiment results demonstrate the architecture's significant enhancement of matrix solution speed,especially suitable for forward and backward substitution resolution of high-dimensional linear matrices in transient circuit simulations.

As novel non-volatile memory,magneto-resistive random access memory (MRAM) has broad application prospects in the field of embedded memory due to its excellent read and write speed and endurance characteristics.However,since the customized design of MRAM usually takes several months to complete,it requires a long design period,which conflicts with the need for a faster design iteration of the system-on-chip.As a tool for quickly generating memory designs,the memory compiler is an effective means to resolve this contradiction.This article starts with the fully customized design process of magnetic random access memory and conducts a survey on the research status of various types of memory compilers.We summarize the current status and challenges of memory compiler design from published work and finally discuss the design methodology of magnetic random access memory compiler.

To solve the problems of poor route ability in flexible printed circuit board,a bus planning algorithm based on pattern routing is proposed,which approximates detailed routing and reduces the precision error between detail routing and bus planning.At the same time,four routing patterns and several fan-out strategies are designed according to manual experience to simulate the possible situation of resource allocation in pin area and arrangement combination of pin areas.Besides,a layer assignment algorithm is designed to comprehensively evaluate the current routing results and the future impact on other nets.According to the restriction that vias are not allowed in the channel,the non-intersecting sequence of the routing topology of the nets in the channel is obtained according to the position sequence of pin areas connected with the channel,which is used as the constraint of the arrangement sequence of the points on the boundary line.Finally,the results in each pattern are comprehensively compared,and the least expensive result is selected as the final bus planning result. Experimental results on industrial cases show that the proposed algorithm realize better performance compared with the existing flexible printed circuit board bus planning algorithm.

With the advancement of integrated circuit technology and the increasing operating frequency of circuits,the impact of Multiple-Input Switching (MIS) effects on circuit static timing analysis has become more prominent,exacerbated by process variations.Traditional Single-Input Switching (SIS) timing library construction methods struggle to handle violations of hold time and setup time.In recent years,several MIS delay models have been proposed to characterize the influence of MIS effects in timing analysis.However,most of these models overlook the impact of input switching time and load on MIS effects,resulting in pessimistic and less accurate predictions.Furthermore,these models individually model each unit without considering the relationship between MIS effects and the transistor-level topology of the unit,leading to decreased accuracy and higher characterization costs.To address these challenges,this paper proposes a novel MIS unit delay prediction framework based on heterogeneous graph neural networks.The transistor-level circuitry of multiple-input units is modeled as a heterogeneous graph,providing a comprehensive and effective representation of factors influencing MIS delay.Multiple-input gate MIS effects are trained as a unified model within this framework.In the context of the 16 nm process,the proposed model is validated on multiple-input units.The experiment results indicate that while reducing the modeling cost to 8.8% of the cost required by the ANN model,the model achieves an average error of only 1.19% for units.Compared to the ANN model,the accuracy has improved 2.05 times.

With the increasing integration of printed circuit board,traditional methods are unable to meet the requirements for size and weight.Copper plating,a crucial step in PCB design,plays a significant role in improving the performance and effectiveness of PCB.To address the numerous circular features on large-scale PCB,a fast shape filling algorithm is proposed.This algorithm utilizes graphic information classification and identifies islands that may arise during the copper plating process.The core idea of the algorithm is as follows:firstly,a large number of features are divided into regions based on their graphical information.Then,clustering is performed based on collision relationships.The outer contour chains and isolated island chains are obtained based on the clustering results.Finally,the result is obtained through the relationship between the contour chains of loops and holes.The algorithm is implemented in a Windows 10 environment with a 3.20 GHz processor and 16 GB memory,and industrial test data is used to validate its performance.The experimental results demonstrate that compared to an open-source copper plating tool based on fitting polygons,the proposed algorithm is independent of the number of polygon edges and achieves a time improvement of approximately 60%.

Currently,analytical methods have achieved the best results for VLSI floorplanning.Module flipping has real applications and can further optimize floorplanning results,but analytical methods cannot handle modules flipping in floorplaning.Therefore,this paper attempts to solve this problem by using a unified analytical method,and proposes a new force,i.e.,the flipping force,for modules flipping.The flipping force can guide each module's flipping to its desired direction based on wire length optimization during the global floorplanning stage.In addition,based on the electrostatic field model,this paper designs a new global floorplanning flow in which special treatment is applied to the density calculation of large-size modules.The aim is to reduce the repulsion of these modules and allow other modules to be placed closer to them,thus achieving a more uniform distribution of modules.To better utilize the whitespace between the floorplan boundary and large modules,a gap handling method is proposed.Finally,a post-floorplanning stage is applied to further optimize the floorplanning result.This stage involves re-optimizing the modules flipping directions using a mixed-integer linear programming,followed by applying our proposed new whitespace redistribution method.The whitespace redistribution method reduces the number of constraints in the linear programming problem and allows multiple rounds of optimization,leading to a more effective reduction of wire length compared to previous methods.The experimental results on HB+ and ami49_x benchmark circuits show that the proposed floorplanning algorithm achieves an average half-perimeter wire length reduction of at least 13.3% and 13.7%,respectively,compared to state-of-the-art floorplanning algorithms.