Figure/Table detail

Bias voltage and temperature dependence of single-event transient in 22 nm FDSOI devices
HUANG Xiaofeng, LI Chenming, WANG Haibin, SUN Yongshu, WANG Liang, GUO Gang, WANG Xueming
Integrated Circuits and Embedded Systems, 2024, 24(7): 30-36.  

工艺参数 数值
沟道长度 22 nm
沟道宽度 80 nm
源/漏掺杂浓度 3.5×1019 cm-3
源/漏轻掺杂浓度 3×1016 cm-3
体区掺杂浓度 5×1015 cm-3
埋氧层厚度 20 nm
栅氧化层厚度 1.25 nm
体区硅膜厚度 6 nm
外延层总厚度 16 nm
Table 1 22 nm FDSOI NMOS model process parameters
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