With the continuous scaling down of transistor technology nodes, achieving timing closure in nanoscale integrated circuits faces severe challenges. Although traditional circuit simulation can evaluate the performance of cell netlists and layouts, its computationally intensive nature results in prohibitively high time costs. This paper proposes a delay-optimization-sensitive cell prediction model that integrates Graph Convolutional Networks (GCN) and Multilayer Perceptrons (MLP). The approach first dynamically adjusts transistor sizes in the netlist based on input signal states, then employs GCN to parse cell netlist structures and generate homogeneous graph representations of transistor connectivity relationships and process parameters. Finally, these topological features are fused with conventional timing characteristics and fed into an MLP to predict cell optimization potential, thereby identifying delay-optimization-sensitive cells. Experimental results demonstrate prediction accuracy rates of 83.2% for the top 10 delay-optimization-sensitive cells with the highest optimization potential and 75.3% for the top 5 such cells. Compared to SPICE simulation, the time required to identify delay-optimization-sensitive cells is reduced from hours to minutes, achieving approximately 600 times acceleration. This method can accurately identify critical optimization targets, provide layout designers with transistor-level optimization parameters, and significantly improve timing closure efficiency.